Manufacturing method of semiconductor device

Abstract

In a method of manufacturing a semiconductor integrated circuit capable of making gate electrode patterns of MOS transistors accurately in compliance with design data, exposure masks of the gate electrode patterns have the prior rendition of pattern shape assessment based on optical simulation. The assessment is carried out by optical simulation of a gate electrode pattern based on pattern data of layout design of the semiconductor integrated circuit. The model-based correction is applied to the optical simulation for the pattern shape assessment (S21-23). The model for the pattern shape assessment is formed by comparing test patterns with light intensity (S14) and defines compensation values correlative to dimensional differences of the light intensity patterns from the test patterns (S15). The test patterns are formed on a basis of test pattern data above different underlays on a test wafer and the light intensity patterns are formed by optical simulation based on test pattern data. This method enables to implement pattern verification in consideration of the influence of underlays on the etching rate, etc. which has not been considered in the conventional optical simulation.

Dependencies are inferred from the claim text.