Method and arrangement for rapid silicon prototyping

A method for designing a semiconductor circuit arrangement comprising:

• providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros;
• using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform and synthesizing a subset of the collection of functional block macros to the programmable circuit;
• and
• extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference chip development, platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software.

A method for designing a semiconductor circuit arrangement, comprising:

• providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros;
• using a collection of functional block macros at one of which is obtained from the deconfigurable and extendible reference-chip development platform;
• extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference-chip development platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software;
• and
• validating a hardware representation of a synthesized subset of functional block macros in the programmable circuit within the extended deconfigurable and extendible reference-chip development platform.

A method, for designing a semiconductor circuit arrangement, comprising:

• providing a deconfigurable and extendible reference-chip development platform that is programmable, and that includes a programmable circuit and a plurality of functional block macros;
• using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible reference-chip development platform;
• extending the deconfigurable and extendible reference-chip development platform, including communicatively coupling at least one external device with the reference-chip development platform, and therein providing an extended deconfigurable and extendible reference-chip development platform that enables co-development and co-validation of hardware and software;
• and
• modifying a subset of the functional block macros and synthesizing the subset of the functional block macros, as modified, to the programmable circuit.

A system for designing a semiconductor circuit arrangement, comprising:

• deconfigurable and extendible means, including a programmable circuit and a plurality of functional block macros, for developing a reference-chip;
• means for using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible means;
• and
• means for extending the deconfigurable and extendible means, including means for communicatively coupling at least one external device with the deconfigurable and extendible means, and therein providing an extended deconfigurable and extendible means that enables co-development and co-validation of hardware and software.

A system, for designing a semiconductor circuit arrangement comprising:

• deconfigurable and extendible means, including a programmable circuit and a plurality of functional block macros for developing a reference-chip;
• means for using a collection of functional block macros at least one of which is obtained from the deconfigurable and extendible means;
• means for extending the deconfigurable and extendible means, including means for communicatively coupling at least one external device with the deconfigurable and extendible means, and therein providing an extended deconfigurable and extendible means that enables co-development and co-validation of hardware and software;
• and
• means for validating a hardware representation of a synthesized subset of functional block macros in the programmable circuit within the extended deconfigurable and extendible means.