Spanning tree method for K-dimensional space
AssigneeLSI Logic Corporation
InventorsAlexander E. Andreev, Vojislav Vukovic
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AssigneeLSI Logic Corporation
InventorsAlexander E. Andreev, Vojislav Vukovic
Estimating the term…
The present invention is directed to a spanning tree method for K dimensional space. To address timing driven buffer insertion and clock routing problems clusters of points must be constructed in 3-dimensional space. The first and second dimensions are coordinates on a plane, while the third dimension is time which is arrival pin time for buffers insertion and clock latency for clock routing. In a first aspect of the present invention, a method includes partitioning an input set of points into a binary tree of partitions so that each leaf partition has maximally a defined number of points. Graph edges are made for the points by connecting each point to its closest points in every of 2K subspaces and the number of graph nodes is then reduced to a predefined value.
A method for partitioning an integrated circuit, comprising:
A method for partitioning an integrated circuit, comprising:
A system, comprising:
A system for partitioning an integrated circuit, comprising:
Dependencies are inferred from the claim text.