Method and configuration for verifying a layout of an integrated circuit and application thereof for fabricating the integrated circuit

A method for fabricating an integrated circuit, which comprises:

• using a computer to create a layout from a circuit design in which the layout has a plurality of interconnection networks having dimensions;
• selecting one of the plurality of the interconnection networks to thereby obtain a selected interconnection network;
• using the computer to verify the layout for the selected interconnection network by calculating a capacitance of the selected interconnection network with respect to others of the plurality of the interconnection networks and calculating the capacitance by performing the following steps:
• determining a filter polygon that surrounds the dimensions of the selected interconnection network;
• providing the filter polygon with dimensions that are enlarged by a predetermined extent relative to the dimensions of the selected interconnection network;
• determining portions of others of the plurality of the interconnection networks that overlap the filter polygon;
• determining a capacitance between the selected interconnection network and the portions of the others of
• the plurality of the interconnection networks that overlap the filter polygon;
• and
• comparing the determined capacitance with the circuit design and optimizing the layout in an event of a deviation;
• and
• after the layout has been verified, fabricating a mask set and using the mask set to fabricate an integrated circuit.

A configuration for using a computer to verify a layout of an integrated circuit, comprising:

• a processor unit configured to calculate a capacitance in a layout, the layout containing a plurality of interconnection layouts which include a selected interconnection network having dimensions, the capacitance being a capacitance of the selected interconnection network with respect to others of the plurality of the interconnection networks;
• the processor unit including means for determining a filter polygon that surrounds the dimensions of the selected interconnection network such that dimensions of the filter polygon are enlarged by a predetermined extent relative to the dimensions of the selected interconnection network;
• the processor unit including means for determining portions of other interconnection networks that overlap the filter polygon;
• and
• the processor unit including means for determining capacitance between the selected interconnection network and the portions of the other interconnection networks which overlap the filter polygon.