System and method for topology based noise estimation of submicron integrated circuit designs
AssigneeSun Microsystems, Inc.
InventorsKathirqamar Aingaran, Stephan Hoerold, Manjunath Haritsa, Farn Wang
Life of this patent
Estimating the term…
Abstract
A tool for computing noise coupled onto victim lines from aggressor lines of an integrated circuit has code for traversing a victim line of the integrated circuit layout to measure its length, its average width, a coupling length, and a harmonic mean of spacing between the victim line and aggressor lines. The tool has code for computing a resistance, estimated coupling capacitance, and total capacitance of the victim line from these parameters.
Claims6
A computer program product for analyzing coupling between signals in a layout of an integrated circuit, comprising:
- machine readable code for traversing a potential victim line of the integrated circuit layout to measure a length of the victim line, an average width of the victim line, a coupling length of the victim line, and a harmonic mean of a spacing between the victim line and any potential aggressor line of the integrated circuit layout that is found within a window distance of the victim line;
- machine readable code for computing a resistance of the victim line from parameters comprising the length of the victim line and the average width of the victim line;
- machine readable code for computing a total capacitance of the victim line from parameters comprising the length of the victim line, the average width of the victim line, and the coupling length of the victim line;
- and
- machine readable code for computing a coupling capacitance of the victim line to a common aggressor from parameters comprising the coupling length of the victim line and the harmonic mean of the spacing between the victim line and the potential aggressor lines within a window distance of the victim line, wherein;
- the machine readable code for computing a total capacitance of the victim line from parameters utilizes parameters further comprising a parameter indicative of portions of the victim line covered by orthogonal lines.
A method for estimating signal coupling from at least one signal line of an integrated circuit into at least one victim signal line of the integrated circuit comprising:
- traversing the victim line of the integrated circuit layout to measure a length of the victim line, an average width of the victim line, a coupling length of the victim line, and a harmonic mean of a spacing between the victim line and any potential aggressor line of the integrated circuit layout that is found within a window distance of the victim line;
- computing a resistance of the victim line from parameters comprising the length of the victim line and the average width of the victim line;
- computing a total capacitance of the victim line from parameters comprising the length of the victim line, the average width of the victim line, and the coupling length of the victim line;
- and
- computing a coupling capacitance of the victim line to a common aggressor from parameters comprising the coupling length of the victim line and the harmonic mean of the spacing between the victim line and the potential aggressor lines within a window distance of the victim line, wherein;
- said computing a total capacitance of the victim line from parameters utilizes parameters further comprising a parameter indicative of portions of the victim line covered by orthogonal lines.
Dependencies are inferred from the claim text.