US 6,665,827 B2Granted

Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system for utilizing the semiconductor integrated circuit

AssigneeMicron Technology, Inc.

InventorsRoland Ochoa, Gregory L. Cowan, Kim M. Pierce

Life of this patent

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Abstract

A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.

Claims11

Dependent claims

A test system comprising:

at least one test station having a first set of test input/output nodes, the at least one test station being configured to transmit a test stimuli via the first set of test input/output nodes;
and
a load board interface comprising:
a second set of test input/output nodes electrically coupled with the first set of test input/output nodes,
a plurality of sets of interface nodes, each interface node of each of the plurality of sets of interface nodes configured for electrical connection with a corresponding input/output node of-a semiconductor integrated circuit, and
a switching structure configured to provide electrical connection between each node of each set of the plurality of sets of interface nodes with a corresponding node of the second set of test input/output nodes while the test system is in an uncompressed mode, and to provide electrical connection between a designated node of each set of the plurality of sets of interface nodes with a corresponding distinct node of the second set of test input/output nodes while the test system is in a compressed mode.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/342,651Filed 14 Jan 2003 · continuation
Priority: 15 Jun 1993
Published: US 2003/0110428 A112 Jun 2003
Granted: 16 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G01R 31/2884
Testing of integrated circuits [IC]: using dedicated test connectors, test elements or test circuits on the IC under test
G01R 31/3187
Functional testing: built-in tests
G01R 31/31905
Tester configuration: interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
G01R 31/3193
Tester hardware, i.e. output processing circuits: with comparison between actual response and known fault free response

Family

Application08/077,182Parent of this continuation-in-part · filed 15 Jun 1993
Application08/353,404Parent of this continuation · filed 9 Dec 1994
Application08/881,946Parent of this continuation · filed 25 Jun 1997
Application09/175,518Parent of this continuation · filed 20 Oct 1998
US 5,864,565 AParent of this continuation · filed 26 Jan 1999
Application09/940,010Parent of this continuation · filed 27 Aug 2001
US 6,314,538 B1Parent of this continuation · filed 6 Nov 2001
US 2003/0110428 A1Pre-grant publication · published 12 Jun 2003
US 6,546,512 B1Parent of this continuation
Application08/353,404Parent of this continuation-in-part
US 6,665,827 B2This patent

From the US filing history. Foreign family members aren’t listed.