Method and apparatus for testing the timing of integrated circuits
AssigneeMicron Technology, Inc.
InventorTimothy B. Cowles
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a first test mode input terminal adapted to disable the output terminal in response to a first test mode signal. A method for testing an integrated circuit, the integrated circuit including a first external pin and an input buffer, includes providing a first external input signal to the first external pin at a first specified time, and disabling the input buffer at a second specified time after the first specified time.
Claims24
An integrated circuit, comprising:
- a first external pin;
- and
- an input buffer connected to said first external pin, wherein said input buffer includes an output terminal and a first test mode input terminal, said input buffer responsive to assertion of a first test mode signal on said first external pin to disable said output terminal;
- wherein said first test mode signal is asserted in a predetermined timed relationship with assertion of an external input signal on said first external pin.
An integrated circuit, comprising:
- a first external pin;
- and
- an input buffer connected to said first external pin, wherein said input buffer includes an output terminal and first and second test mode input terminals, said first and second test mode input terminals respectively responsive to first and second test mode signals to disable said output terminal;
- a second external pin adapted to receive an external clock signal;
- and
- a delay element connected to said second external pin for producing a delayed clock signal, said delay element being coupled to said second test mode input terminal;
- a first transistor connected to a voltage source, a gate input of said first transistor being connected to the first test mode input terminal;
- a second transistor connected to the first transistor and the output terminal, a gate input of said second transistor being connected to the input terminal;
- a third transistor connected to said output terminal, a gate input of said third transistor being connected to said input terminal;
- and
- a fourth transistor connected between said third output terminal and ground, a gate input of said fourth transistor being connected to said second test mode input terminal and
- a fifth transistor coupled between said output terminal and a voltage source, said fifth transistor coupling said output terminal to said voltage source in response to said second test mode signal.
Dependencies are inferred from the claim text.