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US 6,665,823 B2Granted
Method and apparatus for monitoring component latency drifts
AssigneeMicron Technology, Inc.
InventorTerry R. Lee
Life of this patent
Estimating the term…
Abstract
A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such as SLDRAMs, that have programmable response times. A response time monitoring circuit in the form of a phase detector includes a plurality of flip-flops with the data inputs commonly connected to receive a response ready signal from a component, such as a memory circuit, in response to a command to perform a task. Each clock input of the flip-flop is connected to a clock signal at a different phase of a response period. The outputs of the flip-flops determine the phase at which the response ready signal was generated by the component.
Claims50
An apparatus for monitoring the latency of a component that generates a ready signal after completing an assigned task, the apparatus comprising:
- control logic adapted to interface with the component;
- and
- a response time measurement circuit connected to the control logic and the component, the response time measurement circuit receiving, concurrently at a plurality of inputs, said ready signal of a component whose response time is being measured after said component has completed an assigned task, said response time measurement circuit utilizing said ready signal received concurrently at said plurality of inputs and a plurality of delayed clock signals to provide a measured response time to the control logic based upon the received ready signal.
A component controller comprising:
- control logic adapted to interface with the component;
- a response time measurement circuit connected to the control logic and the component for detecting an excessive latency drift of the component in responding to a command and providing an excessive latency drift signal to the control logic;
- and
- a local memory connected to the control logic;
- wherein the control logic is adapted to store information on the component in the local memory when an excessive latency drift signal is received, said information comprising an identification code of the component and the time at which the excessive latency drift signal is provided to the control logic.
2 more elements
A memory controller comprising:
- control logic adapted to interface with a memory component and to generate a response window signal when the memory component is commanded to retrieve data therein;
- an offset clock generator connected to receive the response window signal for generating a plurality of phase clock signals;
- a phase detector comprising a plurality of transparent latches each having a data input, a data output, and a clock input, the clock input of each transparent latch being connected to receive a respective phase clock signal from the offset clock generator, and the data input of each transparent latch being connected to receive a data ready signal from the memory component, the data ready signal being provided by said memory component when the data is available;
- a logic circuit having an input connected to an output of the transparent latches and an output connected to the control logic for generating an excess latency drift signal;
- and
- a local memory connected to the control logic for storing component information for a memory component which caused the excess latency drift signal to be generated.
3 more elements
A computer system comprising:
- a processor;
- a memory component;
- and
- a memory control system connected to and operative with the processor and the memory component, the memory control system comprising:
- control logic adapted to communicate with the memory component;
- a response time measurement circuit connected to the control logic and the component for detecting an excessive latency drift of the component in responding to a command and providing an excessive latency drift signal to the control logic;
- and
- a local memory connected to the control logic;
- wherein the control logic is adapted to store information on the component in the local memory when an excessive latency drift signal is received, said component information comprising an identification code of the component and the time at which the excessive latency drift signal is provided to the control logic.
6 more elements
A computer system comprising:
- a processor;
- a memory component;
- and
- a memory control system connected to and operative with the processor and the memory component, the memory control system comprising:
- control logic adapted to interface with a memory component and to provide a response window signal at the start of a response window;
- an offset clock generator connected to receive the response window signal for generating a plurality of phase clock signals;
- a phase detector comprising a plurality of transparent latches each having a data input, a data output, and a clock input, the clock input of each transparent latch being connected to receive a respective phase clock signal from the offset clock generator, and the data input of each transparent latch being connected to receive a data ready signal from the memory component;
- a logic circuit having an input connected to a data output of at least one of the transparent latches and an output connected to the control logic for generating an excess latency drift signal;
- and
- a local memory connected to the control logic;
- wherein the control logic is adapted to store information pertaining to the component causing the excess latency drift signal to be generated.
8 more elements
A component controller comprising:
- control logic adapted to interface with the component;
- a response time measurement circuit connected to the control logic and the component for detecting an excessive latency drift and providing an excessive latency drift signal to the control logic;
- and
- a local memory connected to the control logic;
- wherein the control logic is adapted to store information on the component in the local memory when an excessive latency drift signal is received and to determine when the latency drift of component indicates that the component may need replacing or relocation.
2 more elements
A memory circuit controller comprising:
- control logic adapted to interface with a plurality of memory circuits;
- a response time measurement circuit connected to the control logic and the memory circuits for detecting an excessive latency drift and providing an excessive latency drift signal to the control logic;
- a local memory connected to the control logic;
- wherein the control logic is adapted to store failure information in the local memory when an excessive latency drift signal is received;
- and
- wherein the control logic is further adapted to determine when the latency drift of one memory circuit indicates that the one memory circuit may need replacing or relocating by calculating the ratio of excessive latency drifts caused by the one memory circuit to the total number of latency drifts, and comparing the ratio to a predetermined threshold.
3 more elements
A computer system comprising:
- a processor;
- an output device connected to the processor;
- a memory component;
- and
- a memory control system connected to and operative with the processor and the memory component, the memory control system comprising:
- control logic adapted to interface with the memory component;
- a response time measurement circuit connected to the control logic and the component for detecting an excessive latency drift and providing an excessive latency drift signal to the control logic;
- and
- a local memory connected to the control logic;
- wherein the control logic is adapted to store information on the component in the local memory when an excessive latency drift signal is received, to determine when the latency drift of the component indicates that the component may need replacing or relocating and to send a message to the processor indicating which component may need replacing or relocating, and wherein the processor outputs the message to the output device.
7 more elements
A computer system comprising:
- a processor;
- an output device connected to the processor;
- a plurality of memory components;
- and
- a memory control system connected to and operative with the processor and the memory components, the memory control system comprising:
- control logic adapted to interface with the memory components;
- a response time measurement circuit connected to the control logic and the memory components for detecting an excessive latency drift and providing an excessive latency drift signal to the control logic;
- a local memory connected to the control logic;
- wherein the control logic is adapted to store failure information in the local memory when an excessive latency drift signal is received;
- and
- wherein the control logic is further adapted to determine when the latency drift of one component indicates that the one component may need replacing or relocating by calculating the ratio of excessive latency drifts caused by the one component to the total number of latency drifts, and comparing the ratio to a predetermined threshold.
8 more elements
A method for monitoring latency drift of a component which generates a ready signal after completing an assigned task, comprising the steps of:
- providing a plurality of transparent latches, each of the latches having a data input, a data output, and a clock input;
- connecting the data input of each transparent latch to receive a ready signal of a component whose response time is being measured;
- connecting the clock input of each transparent latch to receive a respective clock signal generated at a different point of a response window such that the data outputs of the transparent latches indicate the respective portion of the response window in which a data ready signal is received;
- and
- detecting the respective data outputs of the transparent latches.
2 more elements
A method for monitoring latency drift of a programmable response time memory component which generates a ready signal after completing a data retrieval operation, comprising the steps of:
- providing a plurality of transparent latches, each of the latches having a data input, a data output, and a clock input;
- connecting the data input of each transparent latch to receive a ready signal of a programmable response time memory component whose response time is being measured;
- connecting the clock input of each transparent latch to receive a respective clock signal generated at a different point of a response window such that the data outputs of the transparent latches indicate the respective portion of the response window in which a data ready signal is received;
- connecting a logic circuit to the data output of at least one transparent latch to generate an excessive latency drift signal;
- observing the respective data outputs of the transparent latches to determine a latency drift when an excessive latency drift signal is received;
- comparing the determined latency drift to a predetermined threshold;
- and
- recalibrating at least one programmable response time memory component when the determined latency drift exceeds the predetermined threshold.
5 more elements
A method of determining when a component may need to be replaced comprising the steps of:
- monitoring latency drifts of a component;
- storing component latency drift information;
- comparing the stored latency drift information to a predetermined threshold;
- and
- indicating a need for replacement when the stored latency drift information exceeds the threshold.
2 more elements
An apparatus for monitoring the latency of a component that generates a ready signal after completing an assigned task, the apparatus comprising:
- control logic adapted to interface with the component;
- and
- a response time measurement circuit, including a plurality of transparent latches, connected to the control logic and the component, each latch of said plurality concurrently receiving said ready signal of a component whose response time is being measured after said component has completed an assigned task, said response time measurement circuit providing a measured response time to the control logic based upon the received ready signal.
Dependencies are inferred from the claim text.