Microcomputer, electronic equipment, and debugging system

A microcomputer having a real-time trace function, said microcomputer comprising:

• a central processing unit for executing an instruction;
• instruction address setting means for setting an instruction address for detecting an execution of a plurality of instructions to be executed by said central processing unit;
• detection signal output means for outputting a detection signal through a single detection signal output terminal, when the execution of said plurality of instructions has been detected;
• said plurality of instructions comprises a first instruction and a second instruction,
• said detection signal output means omits outputting a detection signal when said first instruction is successively executed after said first instruction is executed and a detection signal is output, and outputs a detection signal only when said second instruction is executed;
• wherein an instruction address that is set by said instruction address setting means comprises an address for specifying at least one of start and end of a trace range;
• said instruction address setting means comprises a plurality of registers for holding instruction address information for detecting the execution of a plurality of instructions, and
• said detection signal output means comprising:
• means for holding a comparison result between an instruction address that was read out previously for instruction execution by said central processing unit and an address that has been held in each of said registers, until the instruction at said previously read-out instruction address is executed, and outputting a detection signal based on said held comparison result when said instruction at said previously read-out instruction address has been executed;
• and
• means for invalidating said comparison result with instructions that were read out before a branch instruction was executed when said executed instruction was a branch instruction.

A microcomputer having a real-time trace function, said microcomputer comprising:

• a central processing unit for executing an instruction;
• instruction address setting means for setting an instruction address for detecting an execution of a plurality of instructions to be executed by said central processing unit;
• detection signal output means for outputting a detection signal through a single detection signal output terminal, when the execution of said plurality of instructions has been detected;
• said plurality of instructions comprises a first instruction and a second instruction,
• said detection signal output means omits outputting a detection signal when said first instruction is successively executed after said first instruction is executed and a detection signal is output, and outputs a detection signal only when said second instruction is executed;
• wherein an instruction address that is set by said instruction address setting means comprises an address for specifying at least one of a start and end of a execution-time measurement range of a program;
• said instruction address setting means comprises a plurality of registers for holding instruction address information for detecting the execution of a plurality of instructions, and
• said detection signal output means comprises:
• means for holding a comparison result between an instruction address that was read out previously for instruction execution by said central processing unit and an address that has been held in each of said registers, until the instruction at said previously read-out instruction address is executed, and outputting a detection signal based on said held comparison result when said instruction at said previously read-out instruction address has been executed;
• and
• means for invalidating said comparison result with instructions that were read out before a branch instruction was executed when said executed instruction was a branch instruction.