Information processing apparatus

An integrated circuit formed of a single chip, said integrated circuit comprising:

• a circuit having a transmission function of receiving data outputted by a first module and transmitting the data together with a first source clock to a second module;
• a reception circuit for receiving data outputted by said second module and a second source clock of said second module synchronized to the data, from said second module;
• a synchronization circuit for connecting said circuit having a transmission function to said reception circuit and synchronizing the receiving of data outputted by said second module at said second source clock to said first source clock;
• and
• an exclusive terminal for inputting and outputting an acknowledge type signal,
• wherein said outputted first source clock is not outputted while the data transmission is inactive.

An integrated circuit included in an information processing system, said information processing system including a module, an integrated circuit, and a bus for connecting said integrated circuit to said module, data being transferred between said module and said integrated circuit via said bus in a source clock synchronous system, comprising:

• a circuit operating according to a first source clock and having a transmission function of transmitting first data together with a first source clock to said module;
• a reception circuit operating according to a second source clock and receiving second data together with said second source clock from said module;
• a synchronization circuit for connecting said circuit having a transmission function to said reception circuit and synchronizing the receiving of data outputted by said module at said second source clock to said first source clock;
• and
• an exclusive terminal for inputting and outputting an acknowledge type signal,
• wherein said first and second source clocks are not outputted while the data transmission is inactive.

An integrated circuit included in an information processing system said information processing including, said integrated circuit connected to a first module, a second module, and a bus for connecting said integrated circuit to said second module, data being transferred between said second module and said integrated circuit via said bus in a source clock synchronous system, comprising:

• a circuit receiving first data outputted by said first module, operating according to a first source clock, and having a transmission function of transmitting said first data together with a first source clock to said second module;
• a reception circuit operating with a second source clock and receiving second data together with said second source clock from said second module;
• a synchronization circuit for connecting said circuit having a transmission function to said reception circuit and synchronizing the receiving of data outputted by said second module at said second source clock to said first source clock;
• and
• an exclusive terminal for inputting and outputting an acknowledge type signal,
• wherein said first and second source clocks are not outputted while the data transmission is inactive.

An integrated circuit formed of a single chip, said integrated circuit comprising:

• a reception circuit portion for receiving data outputted by a transfer source module and a first source clock of said transfer source module synchronized to said data;
• a circuit portion operating according to a second source clock of said integrated circuit;
• a synchronization circuit for synchronizing the receiving of said data at said first source clock as received by said reception circuit portion to said second source clock of said integrated circuit;
• and
• an exclusive terminal for inputting and outputting an acknowledge type signal,
• wherein said source clock is not outputted while the data transmission is inactive.