Resetting a programmable processor
AssigneesIntel Corporation, Analog Devices, Inc.
InventorsCharles P. Roth, Ravi P. Singh, Gregory A. Overkamp
Life of this patent
Estimating the term…
Abstract
In one embodiment, a pipelined processor includes a reset unit that provides an output reset signal to at least one stage of the pipeline. The reset unit is adapted to detect at least a hard reset request, a soft reset request and an emulation reset request. The pipeline comprises N stages and the reset unit asserts the reset signal for at least N cycles of a clock after the reset request has been cleared. Each stage if the pipeline has a storage circuit for storing a corresponding valid bit. At least one of the storage circuits is cleared in response to the reset signal. In addition, the reset unit handles the reset request as a reset event having an assigned priority.
Claims45
A method comprising:
- receiving a request to reset a pipelined processor;
- clearing a valid bit within a stage of the pipelined processor in response to the reset request;
- and
- propagating the cleared valid bit to subsequent stages of the pipelined processor.
A method comprising:
- receiving a request to reset a pipelined processor;
- and
- handling the reset request as a reset event having an assigned priority.
An apparatus comprising:
- an execution pipeline having a plurality of stages, wherein the stages include storage circuits for storing valid bits;
- a reset unit having an output reset signal coupled to the execution pipeline to clear the valid bit of at least one of the storage circuits;
- and
- a control unit adapted to propagate the cleared valid bit through the storage circuits of the execution pipeline.
A programmable processor comprising:
- an event handler having an event status register (IPEND) adapted to process a reset request as an event having an assigned priority, wherein the reset request is one of a hard reset request and a soft reset request;
- and
- a reset unit adapted to output a system reset signal when the event handler accepts the reset event.
A method comprising:
- receiving a request to reset a processor having an N stage pipeline;
- generating a reset signal in response to the reset request;
- and
- synchronously asserting the reset signal for N cycles of a clock after the reset request is cleared.
A method comprising:
- receiving a request to reset a processor;
- updating a bit within an event pending register to indicate a reset event is currently pending;
- updating a bit within an event status register when an event handler accepts the reset event;
- asserting a reset signal in response to the accepted reset event;
- invoking a reset service routine when the reset signal is deasserted.
A system comprising:
- a memory device;
- a processor coupled to the memory device, wherein the processor includes an event handler adapted to process a reset request as an event having an assigned priority, wherein the reset request is one of a hard reset request and a soft reset request.
Dependencies are inferred from the claim text.