Data reordering mechanism for data transfer in computer systems
AssigneeIntel Corporation
InventorsAltug Koker, Russell W. Dyer
Life of this patent
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Abstract
A device to change the ordering of datums in a packet from a storage device to a pre-determined ordering according to their addresses. The device has a first circuit to receive and process address information to determine a data ordering of data associated with the address information; and a second circuit to reorder the data into ordered packets in the predetermined ordering. This device can be used to efficiently transfer graphic data through the AGP bus in a computer.
Claims17
A computer system, comprising a computer processor, a data storage device, a computer device to process data, and a chipset coupled to said computer processor, said data storage device, and said computer device as a communication hub to control data transfer, said chipset comprising:
- an input data circuit to process address information in received data associated with data addresses in said storage device to determine a received data ordering of the received data based on the data addresses in said storage device, and
- a reordering circuit coupled to said input data circuit to output data in a predetermined ordering without changing the address information of the data regardless said received data ordering, said recording circuit operable to reorder received data into ordered packets in said predetermined ordering when the received data ordering is different.
A method, comprising:
- using a chipset to transfer data from a storage device to a computer device inside a computer, wherein transferred data packets are in different received data orderings based on data addresses in the storage device;
- and
- within the chipset, causing data received from the storage device to be reordered into ordered packets each in a predetermined ordering without changing the address information whenever the received data ordering is different from the
- predetermined ordering so that each output data from the chipset is in the predetermined ordering.
Dependencies are inferred from the claim text.