Method and apparatus for preventing unauthorized access of memory devices

A system for coupling a memory device to a data processing device so that said data processing device can communicate with said memory device, said memory device comprising:

• a memory core comprising a plurality of memory locations and a first plurality of signal paths for communicating signals between said memory core and said data processing device;
• a first plurality of signal terminals for coupling said first plurality of signal paths to said data processing device at an interface;
• a first programmable logic circuit coupled between said first signal terminals and said first signal paths and adapted to permit programming of the connection of the signal terminals of said first plurality of signal terminals to the signal paths of said first plurality of signal paths;
• and
• said data processing device comprising:
• data processing circuitry including a second plurality of signal paths corresponding to said first plurality of signal paths;
• and
• a second plurality of signal terminals adapted to couple said second plurality of signal paths to said memory device at said interface;
• and
• a second programmable logic circuit coupled between said second plurality of signal paths and said second plurality of signal terminals, said second programmable logic device adapted to permit programming of the connection of said signal terminals of said second plurality of signal terminals to said signal paths of said second plurality of signal paths;
• wherein said first and second programmable logic circuits can be programmed complementarily so that said interface is non-standard, yet said signals are communicated between signal paths of said first plurality of signal paths and said corresponding signal paths of said second plurality of signal paths without alteration.

A method of preventing unauthorized access of a memory device adapted to interface to a data processing device, said memory device having a memory core and a first plurality of signal paths for conveying signals between said memory core and said data processing device and a first plurality of signal terminals for coupling to said data processing device, said data processing device having data processing circuitry including a second plurality of signal paths corresponding to said first plurality of signal paths and a second plurality of signal terminals adapted to physically couple to said first plurality of signal terminals of said memory device at an interface, said method comprising the steps of:

• providing a first programmable logic circuit between said first signal terminals and said first signal paths of said memory device and adapted to permit programming of the connection of the signal terminals of said first plurality of signal terminals to said signal paths of said first plurality of signal paths;
• providing a second programmable logic circuit between said second plurality of signal paths and said second plurality of signal terminals of said data processing device, each terminal of said second plurality of signal terminals corresponding to one of said signal paths, said second programmable logic device adapted to permit programming of the connection of the signal terminals of said second plurality of signal terminals to said signal paths of said second plurality of signal paths;
• and
• programming said first and second programmable logic circuits complementarily so that said interface is non-standard, yet said signals are communicated between said signal paths and said corresponding signal paths of said second plurality of signal paths without alteration.

A computer program product in a computer readable medium for preventing unauthorized access of a memory device adapted to interface to a data processing device, said memory device having a memory core with a first plurality of signal paths for conveying signals between said memory core and said data processing device, a first plurality of signal terminals for interfacing to said data processing device at an interface and a first programmable logic circuit between said first signal terminals and said first signal paths, said data processing device having data processing circuitry including a second plurality of signal paths corresponding to said first plurality of signal paths, a second plurality of signal terminals adapted to be coupled to said first plurality of signal terminals of said memory device at said interface and a second programmable logic circuit between said second plurality of signal paths and said second plurality of signal terminals, said computer program product comprising:

• first instructions for programming said first programmable logic circuit so as to couple individual signal paths of said first plurality of signal paths to individual signal terminals of said first plurality of signal terminals through said first programmable logic circuit so that signals at said interface are non-standard;
• and
• second instructions for programming said second programmable logic circuit so as to couple individual signal paths of said second plurality of signal paths to individual signal terminals of said second plurality of signal terminals through said second programmable logic circuit in a complementary scheme relative to said first programmable logic circuit, whereby said interface is nonstandard, yet said signals are communicated between said signal paths of said first plurality of signal paths and said corresponding signal paths of said second plurality of signal paths without alteration.