Apparatus and method for speculative prefetching after data cache misses

A processor having a normal mode and a speculative prefetching mode, the processor operable in the speculative prefetching mode after a data cache miss, comprising:

• a first data cache for storing data when the processor operates in the normal mode;
• a second data cache for storing data in response to a store instruction when the processor operates in the speculative prefetching mode;
• a first register for storing data when the processor operates in the normal mode;
• a second register for storing data in response to a load instruction when the processor operates in the speculative prefetching mode, the second register further having a trash bit for indicating whether the second register contains arbitrary data;
• and
• control logic for setting the trash bit of the second register when a source operand for the load instruction depends on the data cache miss.

A processor having a normal mode and a speculative prefetching mode, the processor operable in the speculative prefetching mode after a data cache miss, comprising:

• a first register for storing data during the normal mode;
• a second register for storing data during the speculative prefetching mode, the second register comprising a first trash bit that indicates whether the second register contains arbitrary data;
• an instruction bus for receiving a stream of instructions including a first instruction and a second instruction;
• control logic for executing the first instruction;
• control logic for initiating a cache fill request provided execution of the first instruction encounters a data cache miss;
• control logic for setting the trash bit of the second register in response to the first instruction and the data cache miss;
• control logic for executing the second instruction in the speculative prefetching mode using the second register in place of the first register;
• a first data cache for storing data during the normal mode;
• and
• a second data cache for storing data in response to a store instruction during the speculative prefetching mode, wherein the second data cache comprises:
• an entry for storing data;
• and
• a second trash bit associated with the entry, the second trash bit for indicating whether the entry contains arbitrary data;
• and
• control logic for setting the second trash bit in the second data cache when a source operand for the second instruction depends on the data cache miss.

A processor having a normal mode and a speculative prefetching mode, the processor operable in the speculative prefetching mode after a data cache miss, comprising:

• a first register for storing data during the normal mode;
• a second register for storing data during the speculative prefetching mode, the second register comprising a first trash bit that indicates whether the second register contains arbitrary data;
• an instruction bus for receiving a stream of instructions including a first instruction and a second instruction;
• control logic for executing the first instruction;
• control logic for initiating a cache fill request provided execution of the first instruction encounters a data cache miss;
• control logic for setting the trash bit of the second register in response to the first instruction and the data cache miss;
• control logic for executing the second instruction in the speculative prefetching mode using the second register in place of the first register;
• and
• control logic operable for updating a branch prediction state for a branch instruction in the speculative prefetching mode provided the branch instruction is not dependent on arbitrary data.

In a processor having a first cache memory for storing data in a normal mode and a second cache memory for storing data in a speculative prefetching mode, a method of performing memory accesses, comprising:

• (a) receiving a first load instruction that calls for transferring a first data into a first register;
• (b) determining whether the first data is present in the first data cache;
• (c) provided the first data is missing from the first data cache, initiating a first cache fill request to retrieve the first data from an external memory, copying a first program counter to a second program counter, and writing an arbitrary data into a special register such that program execution continues with the second program counter and the arbitrary data;
• (d) before the first cache fill request is completed, receiving a second load instruction that calls for transferring a second data into a second register, and determining whether the second data is present in the first data cache and the second data cache;
• (e) provided the second data is missing from the first data cache and the second data cache, initiating a second cache fill request to retrieve the second data from an external memory;
• (f) after the first cache fill request is completed, resuming program execution using the first program counter and ignoring the arbitrary data stored in the second register and in the second cache memory;
• and
• (g) re-executing the second load instruction, wherein retrieval time of the second data is reduced as the second cache fill request has been previously initiated.