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US 6,665,775 B1Granted
Cache dynamically configured for simultaneous accesses by multiple computing engines
AssigneeIntel Corporation
InventorsSubramaniam Maiyuran, Salvador Palanca
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Abstract
A cache has an array with single ported cells and is dynamically accessible simultaneously by multiple computing engines. In a further embodiment, the cache also has a tag array including a first address input, a second address input, and a shared mode input, and a data array electrically coupled to the tag array and including a first address input, a second address input, and a shared mode input.
Claims27
A cache, comprising:
- a tag array comprising a first address input to receive an address from a first computing engine, a second address input to receive an address from a second computing engine, a shared mode input to receive a shared mode value, and a plurality of tag array lines arranged into a plurality of sets and ways, wherein a first subdivision of said sets of tag array lines in each of said ways may be dynamically allocated either for exclusive access by the first computing engine or for exclusive access by the second computing engine, wherein said allocation is based upon the shared mode value received at the shared mode input, wherein the plurality of sets of tag array lines in the tag array also includes a second subdivision of said sets, and wherein sets of tag array lines in the second subdivision are allocated for exclusive access by the first computing engine regardless of the shared mode value received at the shared mode input;
- and
- a data array electrically coupled to the tag array.
A system comprising:
- a first computing engine;
- a second computing engine;
- and
- a cache comprising:
- a tag array comprising a first address input to receive an address from the first computing engine, a second address input to receive an address from the second computing engine, a shared mode input to receive a shared mode value, and a plurality of tag array lines arranged into sets and ways, wherein a first subdivision of said sets of tag array lines in each of said ways may be dynamically allocated either for exclusive access by the first computing engine or for exclusive access by the second computing engine, and wherein said allocation is based upon the shared mode value received at the shared mode input, wherein the plurality of sets of tag array lines in the tag array also includes a second subdivision of said sets, and wherein sets of tag array lines in the second subdivision are allocated for exclusive access by the first computing engine regardless of the shared mode value received at the shared mode input;
- and
- a data array electrically coupled to the tag array.
4 more elements
A method of allocating subdivisions in a cache which comprises a plurality of locations arranged by set and way, the method comprising:
- receiving a first address from a first computing engine, wherein the first address comprises a plurality of bits, wherein said plurality of bits include a set field and a tag field, wherein said set field includes a first bit;
- receiving a second address from a second computing engine;
- receiving a shared mode value;
- dynamically allocating a first subdivision of sets of locations in each way in a tag array in the cache for exclusive access by the first computing engine or for exclusive access by the second computing engine based upon the received shared mode value;
- dynamically allocating a first subdivision of sets of lines in a data array in the cache for exclusive access by the first computing engine or for exclusive access by the second computing engine based upon the received shared mode value;
- selecting a set in the tag array based on said first address without using said first bit in the set field of said first address;
- and
- identifying a way in the cache based in part upon said first bit in the set field of said first address.
5 more elements
A cache, comprising:
- a tag array comprising a first address input to receive an address from a first computing engine, a second address input to receive an address from a second computing engine, a shared mode input to receive a shared mode value, and a plurality of tag array lines arranged into a plurality of sets and ways, wherein a first subdivision of said sets of tag array lines in each of said ways may be dynamically allocated either for exclusive access by the first computing engine or for exclusive access by the second computing engine, wherein said allocation is based upon the shared mode value received at the shared mode input, wherein the first address input receives an address that comprises a plurality of bits, wherein said plurality of bits include a set field and a tag field, wherein said set field includes a first bit, and wherein the tag array contains a row decoder and a selector to select a set in the tag array based on the address received at the first address input without using said first bit in the set field of said received address, wherein the tag array contains logic to identify a way in the cache based in part upon said first bit in the set field of the address received at the first address input;
- and
- a data array electrically coupled to the tag array.
Dependencies are inferred from the claim text.