Vector and scalar data cache for a vector multiprocessor

A method for caching data in a computer system, the system having a common memory having a plurality of sections, and a scalar/vector processor coupled to the memory using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory is associated with each address bus and at least one of the sections of the memory is associated with each read-data bus, the processor having a plurality of scalar registers and a plurality of vector registers and operating on instructions which provide a reference address to a data word, the processor having a scalar/vector cache unit, the cache unit including a cache array;

• the method comprising:
• transmitting a series of addresses on each of the plurality of address busses requesting that a plurality read-data values be placed on each of the plurality of read-data busses;
• for each address on each address bus, tracking both an address in the cache array to which a read-data value will be placed when the read-data value is returned from the memory, and
• a destination code that specifies which of the scalar registers and vector registers into which the read-data value is to be loaded when the read-data value is returned from the memory.

A computer system comprising:

• a common memory, the memory having a plurality of sections;
• and
• a plurality of scalar/vector processors coupled to the memory using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory is associated with each address bus and at least one of the sections of the memory is associated with each read-data bus, the processor having a plurality of scalar registers and a plurality of vector registers and operating on instructions which provide a reference address to a data word, each processor comprising:
• a scalar/vector cache unit, the cache unit including:
• a cache array that caches data for vector fetches and scalar fetches, and wherein the cache unit fetches a different amount of data into cache array based on whether a read-data operation is for a scalar register or a vector register.

A computer system comprising:

• a common memory, the memory having a plurality of sections;
• and
• a plurality of scalar/vector processors coupled to the memory using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory is associated with each address bus and at least one of the sections of the memory is associated with each read-data bus, the processor having a plurality of scalar registers and a plurality of vector registers and operating on instructions which provide a reference address to a data word, each processor comprising:
• a scalar/vector cache unit, the cache unit including:
• a cache array that caches data for vector fetches, scalar fetches, wherein the cache unit fetches a different amount of data into cache array based on whether a read-data operation is for a scalar register or a vector register,
• a FIFO unit that tracks an address in the cache array to which a read-data value will be placed when the read-data value is returned from the memory, wherein the memory includes a plurality of sections, the FIFO unit includes a number of FIFOs equal to the number of sections, and one of the FIFOs is associated with each one of the sections.