Method and apparatus for dynamically masking an N-bit memory array having individually programmable cells

In a method of programming an N-bit memory array, whose cells are individually programmable by first bits that exhibit a predetermined logic state, in such a manner that no more than K cells are simultaneously programmed, the steps of

• counting the number of first bits in a first N-bit programming byte;
• if the number of first bits counted in the first byte exceeds K, generating a second N-bit programming byte which replicates the bit pattern of the first byte up to the Kth first bit and thereafter exhibits bits whose logic state is different from that of the first bits;
• applying the bit pattern of the second byte to the respective cells of the array;
• if the number of first bits counted in the first byte exceeds K, generating a third N-bit programming byte which replicates the bit pattern of the first byte after the Kth first bit but otherwise exhibits bits whose logic state is different from that of the first bits;
• and
• applying the bit pattern of the third byte to the respective cells of the array.

Apparatus for dynamically masking an N-bit memory array whose cells are individually programmable by first bits that exhibit a predetermined logic state, which comprises:

• an accumulator having an input for receiving N-bit bytes and an output that exhibits one of two complementary logic states, means for counting the bits of each byte applied to the input of the accumulator, and means for switching the logic state of the accumulator output if and when the counted number of first bits of the byte applied to the accumulator input during a current byte cycle exceeds K;
• switching means for normally applying arbitrary N-bit bytes to the accumulator input, the switching means being operable to apply to the accumulator input, during a subsequent byte cycle, a replica of the byte applied to the accumulator input during the current byte cycle;
• means for operating the switching means when the logic state of the accumulator output is switched;
• a coincidence circuit having a data input, a control input and an output;
• means for applying, to the data input of the coincidence circuit;
• N-bit bytes applied to the accumulator input by the switching means;
• means for applying the output of the accumulator to the control input of the coincidence circuit;
• and
• means for coupling the output of the coincidence circuit to the respective cells of the array.

Apparatus for dynamically masking an N-bit memory array whose cells are individually programmable by first bits that exhibit a predetermined logic state, which comprises:

• an accumulator having an input for receiving N-bit bytes and an output that exhibits one of two complementary logic states, means for counting the bits of each byte applied to the input of the accumulator, and means for switching the logic state of the accumulator output if and when the counted number of first bits in the incoming byte exceeds K;
• a buffer circuit comprising a switch having a first data input for receiving N-bit bytes, a memory for storing such bytes, a second data input for receiving bytes stored in the memory, a control input operable between two complementary logic states, an output normally connected to the first data input, and means for connecting the output of the buffer circuit to the second data input upon a change in logic state of the control input;
• a coincidence circuit having first and second inputs and an output;
• means for applying the output of the buffer circuit to the input of the accumulator and to the first input of the coincidence circuit;
• means for applying the output of the accumulator to the control input of the buffer circuit and the second input of the coincidence circuit;
• and
• means for coupling the output of the coincidence circuit to the respective cells of the array.

A method of processing a data segment into a succession of N-bit bytes none of which has more than an individually selected number of bits representing a predetermined value, which comprises the steps of:

• extracting, from the data segment, a first subset whose bit pattern contains K first bits representing the same value, where K is no greater than N;
• mapping such first subset into a first N-bit byte whose bit pattern replicates the bit pattern of the first subset up to the position of the Kth first bit and otherwise exhibits bits whose value is arbitrarily set;
• extracting, from the data segment, a second subset which commences at the bit position immediately after that of the Kth first bit of the first subset and which has a bit pattern containing M first bits, where M is no greater than N;
• and
• mapping such second subset into a second N-bit byte whose bit pattern replicates the bit pattern of the second subset up to the position of the Mth first bit and otherwise exhibits bits whose value is arbitrarily set.

A method of processing a data segment into a succession of N-bit bytes none of which has more than an individually selected number of first bits exhibiting a predetermined logic state, which comprises the steps of:

• extracting, from the data segment, a first subset whose bit pattern contains K first bits, where K is no greater than N;
• mapping such first subset into a first N-bit byte whose bit pattern replicates the bit pattern of the first subset up to the position of the Kth first bit and otherwise exhibits bits whose logic state is different from that of the first bits;
• extracting, from the data segment, a second subset which commences at the bit position immediately after that of the Kth first bit of the first subset and which has a bit pattern containing M first bits, where M is no greater than N;
• and
• mapping such second subset into a second N-bit byte whose bit pattern replicates the bit pattern of the second subset up to the position of the Mth first bit and otherwise exhibits bits whose logic state is different from that of the first bits.

A method of programming an N-bit memory array, whose cells are individually programmable by first programming bits that exhibit a predetermined logic state using the bit pattern of an arbitrary N-bit first byte, in such a manner that no more than K cells are simultaneously programmed, which comprises the steps of:

• extracting, from the first byte, successive subsets each of whose bit patterns contains an individually selected number, no greater than K, of first programming bits;
• mapping each such subset into a separate N-bit auxiliary byte whose bit pattern replicates the bit pattern of the corresponding subset up to the position of the last of the selected number of first programming bits in such subset, and otherwise contains bits exhibiting a logic state different from that of the first programming bits;
• and
• applying each auxiliary byte to the array.