Programmer initiated cache block operations

A data processing system comprising:

• a central processing unit executing program instructions to manipulate data;
• at least one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit;
• and
• a cache operation unit connected to said at least one cache performing a program controlled cache state operation on a program designated address range, said cache operation unit including
• a base address register loadable by said central processing unit,
• a word count register loadable by said central processing unit,
• wherein said program designated address range of said program controlled cache state operations are from a base address corresponding to data stored in said base address register for a number of words of corresponding to data stored in said word count register;
• and
• wherein said program controlled cache state operation triggers upon loading said word count register.

A data processing system comprising:

• a central processing unit executing program instructions to manipulate data;
• at least one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit;
• and
• a cache operation unit connected to said at least one cache performing a program controlled cache state operation on a program designated address range, said cache operation unit including
• a base address register loadable by said central processing unit,
• a word count register loadable by said central processing unit,
• a two's complement unit connected to said base address register forming a two's complement of M least significant bits of said base address register, where said at least one cache has entries of 2M data words,
• a least number selector connected to said word count register and said two's complement unit producing an output equal to the least of said two's complement of M least significant bits of said base address register, said word count stored in said word count register and 2M,
• an incrementer connected to said base address register and said least number selector for incrementing said base address register by said output of said least number selector, and
• a decrementer connected to said word count register and said least number selector for decrementing said word register by said output of said least number selector;
• and
• wherein said program designated address range of said program controlled cache state operations are from a base address corresponding to data stored in said base address register for a number of words of corresponding to data stored in said word count register.

A data processing system comprising:

• a central processing unit executing program instructions to manipulate data;
• at least one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit;
• and
• a cache operation unit connected to said at least one cache performing a program controlled cache state operation on a program designated address range, said cache operation unit including
• a base address register loadable by said central processing unit,
• a word count register loadable by said central processing unit,
• an incrementer connected to said base address register for incrementing said base address register by 2M, where said at least one cache has entries of 2M data words, and
• a decrementer connected to said word count register and said least number selector for decrementing said word register by 2M;
• and
• wherein said program designated address range of said program controlled cache state operations are from a base address corresponding to data stored in said base address register for a number of words of corresponding to data stored in said word count register.

A data processing system comprising:

• a central processing unit executing program instructions to manipulate data;
• at least one cache connected to said central processing unit temporarily storing in a plurality of cache lines at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit, each cache line including a tag indicating a memory address of said program instruction or said data stored therein;
• and
• a cache operation unit connected to said at least one cache locking each cache line of said at least one cache currently caching data from a program designated address range encompassing a plurality of cache lines.

A data processing system comprising:

• a central processing unit executing program instructions to manipulate data;
• at least one cache connected to said central processing unit temporarily storing in a plurality of cache lines at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit, each cache line including a tag indicating a memory address of said program instruction or said data stored therein;
• and
• a cache operation unit connected to said at least one cache performing a program controlled cache state operation on a program designated address range encompassing a plurality of cache lines, said cache operation unit being further connected to said central processing unit and generating an interrupt to said central processing unit upon completion of said program controlled cache state operation.

A data processing system comprising:

• a central processing unit executing program instructions to manipulate data;
• at least one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit;
• and
• a cache operation unit connected to said at least one cache locking each cache line of said at least one cache currently caching data from a program designated address range encompassing a plurality of cache lines, said cache operation unit including
• a base address register loadable by said central processing unit,
• a word count register loadable by said central processing unit,
• wherein said locking each cache line of said at least one cache currently caching data from said program designated address range encompassing a plurality of cache lines are from a base address corresponding to data stored in said base address register for a number of words of corresponding to data stored in said word count register.

A data processing system comprising:

• a central processing unit executing program instructions to manipulate data;
• at least one cache connected to said central processing unit temporarily storing at least one of program instructions for execution by said central processing unit and data for manipulation by said central processing unit;
• a cache operation unit connected to said at least one cache performing a program controlled cache state operation on a program designated address range, said cache operation unit including
• a base address register loadable by said central processing unit,
• a word count register loadable by said central processing unit,
• said base address register and said word count register consisting of memory mapped control registers at addresses non-cacheable in said at least one cache;
• and
• wherein said program designated address range of said program controlled cache state operations are from a base address corresponding to data stored in said base address register for a number of words of corresponding to data stored in said word count register.