US 6,665,766 B1 · Adaptable configuration interface for a programmable logic device

Abstract

An adaptable configuration interface for a programmable logic device (PLD). A PLD includes a plurality of configuration pins and circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD. A register that is external to the PLD is connected to the configuration pins of the PLD, and a processor is coupled to the register. A first set of routines, each executable on the processor, are configured to read and write values from and to the register. A second set of routines, each executable on the processor, provide an application programming interface for the configuration and readback of data from the PLD via the first set of routines. The layered structure of the interface routines aids in incrementally changing from a software controlled configuration interface to an interface that is a combination of hardware and software.

Claims12

Dependent claims

A configuration interface arrangement for a programmable logic device (PLD) having a plurality of configuration pins, the configuration pins including one or more input/output data pins, a plurality of configuration control pins including a read/write control pin, and a configuration clock pin, the PLD having circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD, the configuration interface arrangement comprising:

a register external to the PLD and including a plurality of memory elements respectively connected to the configuration pins of the PLD;
a processor coupled to the register;
a first set of routines executable on the processor and configured to read and write bit values from and to the register;
and
a second set of routines executable on the processor, a first one of the second set of routines configured to write data to the PLD via calls to the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the write protocol.

2 more elements

A method for selectably configuring and reading back data from a programmable logic device (PLD) having a plurality of configuration pins, the configuration pins including one or more input/output data pins, a plurality of configuration control pins including a read/write control pin, and a configuration clock pin, the PLD having circuitry implementing read and write protocols for reading data from and writing configuration data to the PLD, comprising:

connecting respective memory elements of a register external to the PLD to the configuration pins of the PLD;
providing a first set of routines executable on a processor, the first set of routines configured to read and write bit values from and to the register responsive to routine calls;
providing a second set of routines executable on the processor, a first one of the second set of routines configured to write data to the PLD via calls to the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the write protocol, and a second one of the second set of routines configured to read data from the PLD via the first set of routines in response to a routine call from a program executing on the processor, and further configured to automatically write bit values to the memory elements connected to the configuration pins as required by the read protocol;
configuring the PLD via a routine call to the first routine;
and
reading back data from the PLD via a routine call to the second routine.

3 more elements

Dependencies are inferred from the claim text.

Adaptable configuration interface for a programmable logic device

Life of this patent

Adaptable configuration interface for a programmable logic device

Life of this patent

Abstract

Claims12