Group shifting and level shifting rotational arbiter system

A system comprising:

• (A) a plurality of hardware resources, the plurality of hardware resources being divided into groups of hardware resources;
• (B) a common resource, the common resource being coupled to the plurality of hardware resources;
• and
• (C) an arbiter, the arbiter being coupled to the plurality of resources, the arbiter controlling which of the plurality of hardware resources has priority to access to the common resource, the arbiter including a group shifting arbiter and a level shifting arbiter, the group shifting arbiter being configured to shift priority among the groups of hardware resources, and the level shifting arbiter being configured to separately shift priority among the hardware resources within each of the groups;
• wherein the group shifting arbiter shifts priority in accordance with a group shifting round robin loop, wherein the level shifting arbiter shifts priority in accordance with a level shifting round robin loop, and wherein the group shifting round robin loop and the level shifting round robin loop cooperate to form a weighted round robin priority scheme in which the frequency with which each hardware resource is granted access to the common resource is determined by (1) the total number of different groups through which the group shifting round robin loop passes, (2) the composition of each group, including the number of hardware resources within each group and the frequency with which hardware resources within each group request access to the common resource, and (3) the placement of the group in which the hardware resource is included relative to the remaining groups including any empty groups, an empty group being a group that does not include any hardware resources.

A method of arbitrating access to a data bus comprising:

• receiving a plurality of access requests for a common resource, the plurality of requests being received from a plurality of hardware resources, the plurality of hardware resources being divided into a plurality of groups including first, second, third and fourth groups;
• determining which of the first, second, third and fourth groups has priority, the group priority determining step being performed in accordance with a group shifting round robin loop that includes the first, second, third and fourth groups;
• determining which of the hardware resources has priority within the group determined to have priority, the resource priority determining step being performed in accordance with a level shifting round robin loop that includes a plurality of the hardware resources within the group determined to have priority;
• and
• wherein the group shifting round robin loop and the level shifting round robin loops cooperate to form a weighted round robin priority scheme in which the frequency with which each hardware resource is granted access to the common resource is determined by (1) the total number of different groups through which the group shifting round robin loop passes, (2) the composition of each group, including the number of hardware resources within each group and the frequency with which hardware resources within each group request access to the common resource, and (3) the placement of the group in which the hardware resource is included relative to the remaining groups including any empty groups, an empty group being a group that does not include any hardware resources.

An arbiter comprising:

• (A) a plurality of hardware resources, the plurality of hardware resources being divided into a plurality of groups;
• (B) a plurality of decoder circuits, the plurality of decoder circuits each receiving a first input indicative of an access request from a respective one of the plurality of hardware resources and a second input indicative of a priority level assigned to the hardware resource, the decoder circuit combining the first and second inputs to produce a decoder circuit output, the decoder circuit output being a binary number comprising a plurality of bits, a bit position of one of the bits corresponding to the priority level assigned to the respective hardware resource, and the on/off state of the bit being indicative of the access request;
• (C) a first combinational logic circuit, the first combinational logic circuit combining the decoder outputs to produce a first combinational logic circuit output, the first combinational logic circuit output being a binary number comprising a plurality of bits, each bit corresponding to a respective one of the plurality of groups of hardware resources, the on/off state of the bit indicating whether the respective one of the plurality of groups of hardware resources includes a hardware resource that is asserting an access request;
• (D) a group shifting arbiter, the group shifting arbiter receiving the first combinational logic circuit output, the group shifting arbiter isolating one of the bits of the first combinational logic circuit output and producing a group shifting arbiter output in which the one of the bits of the first combinational logic circuit output is set to one state and the remaining bits are set to a different state, the group shifting arbiter output indicating which of the plurality of groups of hardware resources has been granted priority;
• (E) an encoder, the encoder receiving the group shifting arbiter output, the encoder producing an encoder output, the encoder output being a binary number having a value that indicates which of the plurality of groups of hardware resources has been granted priority;
• (F) a plurality of comparator circuits, each of the comparator circuits comparing the encoder output with the second input indicative of a priority level assigned to the hardware resource, the comparator circuits each producing a comparator circuit output, the comparator outputs each indicating whether a respective one of the plurality of hardware resources is assigned the same priority level as the group to which priority has been granted;
• (G) a second combinational logic circuit, the second combinational logic circuit combining the encoder outputs to produce a second combinational logic circuit output, the second combinational logic circuit output being a binary number comprising a plurality of bits, each bit corresponding to a respective one of the plurality of hardware resources, the on/off state of the bit indicating whether the respective one of the plurality of hardware resources is asserting an access request and is included in the group to which priority has been granted;
• and
• (H) a level shifting arbiter, the level shifting arbiter receiving the second combinational logic circuit output, the level shifting arbiter isolating one of the bits of the second combinational logic circuit output and producing a level shifting arbiter output in which the one of the bits of the second combinational logic circuit output is set to one state and the remaining bits are set to a different state, the level shifting arbiter output being a priority grant to one of the plurality of hardware resources;
• wherein the group shifting arbiter shifts priority in accordance with a group shifting round robin loop, wherein the level shifting arbiter shifts priority in accordance with a level shifting round robin loop, and wherein the group shifting round robin loop and the level shifting round robin loop cooperate to form a weighted round robin priority scheme in which the frequency with which each hardware resource is granted access to the common resource is determined by (1) the total number of different groups through which the group shifting round robin loop passes, (2) the composition of each group, including the number of hardware resources within each group and the frequency with which hardware resources within each group request access to the common resource, and (3) the placement of the group in which the hardware resource is included relative to the remaining groups including any empty groups, an empty group being a group that does not include any hardware resources.

A system-on-chip integrated circuit comprising:

• (A) a plurality of hardware resources, the plurality of hardware resources being divided into groups of hardware resources;
• (B) a common resource, the common resource being coupled to the plurality of hardware resources;
• and
• (C) an arbiter, the arbiter being coupled to the plurality of resources, the arbiter controlling which of the plurality of hardware resources has priority to access to the common resource, the arbiter including a group shifting arbiter and a level shifting arbiter, the group shifting arbiter being configured to shift priority among the groups of hardware resources, and the level shifting arbiter being configured to separately shift priority among the hardware resources within each of the groups;
• wherein the group shifting arbiter has an active mode of operation and an inactive mode of operation;
• wherein, in the active mode of operation, the group shifting arbiter shifts priority among the groups of hardware resources;
• and
• wherein, in the inactive mode of operation, priority among the groups of hardware resources remains fixed.

A system comprising:

• (A) a plurality of hardware resources, the plurality of hardware resources being divided into groups of hardware resources;
• (B) a common resource, the common resource being coupled to the plurality of hardware resources;
• and
• (C) an arbiter, the arbiter being coupled to the plurality of resources, the arbiter controlling which of the plurality of hardware resources has priority to access to the common resource, the arbiter including a group arbiter and a level arbiter, the group arbiter being configured to assign priority among the groups of hardware resources, and the level arbiter being configured to separately assign priority among the hardware resources within each of the groups;
• wherein the group arbiter and the level arbiter cooperate to form a weighted priority scheme in which the frequency with which each hardware resource is granted access to the common resource is determined by the total number of different groups and the composition of each group, including the number of hardware resources within each group and the frequency with which hardware resources within each group request access to the common resource.

A system comprising:

• (A) a plurality of hardware resources, the plurality of hardware resources being divided into groups of hardware resources;
• (B) a common resource, the common resource being coupled to the plurality of hardware resources;
• and
• (C) an arbiter, the arbiter being coupled to the plurality of resources, the arbiter controlling which of the plurality of hardware resources has priority to access to the common resource, the arbiter including a group arbiter and a level arbiter, the group arbiter being configured to assign among the groups of hardware resources, and the level arbiter being configured to separately assign priority among the hardware resources within each of the groups;
• wherein the group arbiter and the level arbiter cooperate to form a weighted priority scheme in which the frequency with which each hardware resource is granted access to the common resource is determined by the total number of different groups and the placement of the group in which the hardware resource is included relative to the remaining groups including any empty groups, an empty group being a group that does not include any hardware resources.