Bus interface unit for reflecting state information for a transfer request to a requesting device

A computer system comprising:

• an input/output bus;
• a peripheral device coupled with the input/output bus to provide a first data transfer request to the input/output bus;
• a host bus;
• a target component coupled with the host bus containing a data associated with the data transfer request;
• and
• a request interface device coupled between the input/output bus and the host bus to facilitate the transfer of the data from the target component to the peripheral device, the device comprising:
• a plurality of data transfer requesters coupled with the input/output bus, the plurality of data transfer requestors including a first data transfer requestor to receive the first data transfer request from the peripheral device, the first data transfer requestor containing request logic to generate a second data transfer request and corresponding state information based on the received first data transfer request;
• a mux/demux device coupled with the plurality of data transfer requestors to receive data transfer requests and corresponding state information from the requesters, including to receive the second data transfer request and corresponding state information from the first data transfer requestor;
• and
• a bus interface unit coupled with the mux/demux device to receive the second data transfer request and corresponding state information, the bus interface unit coupled with the host bus and the target component, wherein the bus interface unit comprises a memory to store the second data transfer request and corresponding state information received from the mux/demux device, and wherein the bus interface unit comprises bus interface unit logic to retrieve the second data transfer request and corresponding state information from the memory, gain access to the host bus, transmit the second data transfer request over the host bus, and contemporaneously provide the state information corresponding to the second data transfer request to the mux/demux device.

A device comprising:

• a plurality of requestors, each of the requesters including,
• a requestor interface, and
• requestor logic to generate transfer requests and associated state information, transmit the transfer requests and the associated state information to a bus interface unit through the requestor interface and a mux/demux device, and receive an indication that a transfer request has been granted from the bus interface unit through the requestor interface and the mux/demux device;
• a first requestor of the plurality of requestors to generate a first transfer request and state information associated with the first transfer request and send the first transfer request and the state information associated with the first transfer request to the bus interface unit through the first requestor interface and the mux/demux device;
• the mux/demux device to,
• transfer the first transfer request and the state information associated with the first transfer request from the first requester to the bus interface unit,
• receive the state information associated with the first transfer request from the bus interface unit along with an indication that the first transfer request has been granted,
• route the received state information associated with the first transfer request and the indication that the first transfer request has been granted to the first requestor;
• and
• the bus interface unit including,
• a first bus interface unit interface coupled with the mux/demux device to receive the first transfer request and the state information associated with the first transfer request,
• a second bus interface unit interface coupled with a host bus,
• a memory to store the first transfer request and the state information associated with the first transfer request, and
• a bus interface unit logic to retrieve the first transfer request and the state information associated with the first transfer request from the memory, gain access to the host bus, transmit the first transfer request over the host bus through the second bus interface unit interface, and contemporaneously reflect the state information associated with the first transfer request back to the mux/demux device through the first bus interface unit interface.