US 6,665,755 B2 · External memory engine selectable pipeline architecture

Abstract

External memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The route switch packet architecture includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

Claims16

Dependent claims

A method for providing external memory services to a multi-thread packet processor comprising:

decoding information data sequences for a data packet within the multi-thread packet processor to determine assigning an operation to one of a first external memory bank and a second external memory bank;
executing a read operation by comparing a read address with addresses stored in a write buffer, initiating a read, and replacing read data with data in the write buffer;
executing a write operation by comparing a write address with addresses stored in a write buffer when the write buffer is enabled, and writing data to a reserved location in the write buffer;
executing an atomic add operation by performing a write operation in the write buffer if there is available space in the write buffer;
executing a lookup operation by indexing into a memory bank based on a base address, a key, and a key length, and conducting flow and memory accesses of the memory bank;
and
returning a result data field to the multi-thread packet processor when one operation is completed.

4 more elements

Dependencies are inferred from the claim text.

External memory engine selectable pipeline architecture

Life of this patent

External memory engine selectable pipeline architecture

Life of this patent

Abstract

Claims16