Bus protocol for efficiently transferring vector data

Abstract

The present invention provides a bus architecture for a data processing system that improves transfers of vector data using a vector transfer unit (VTU). An external bus is coupled between the vector transfer unit and the memory. The external bus includes a system command bus that is used to transmit a data transfer command. The command is based on a corresponding vector transfer instruction in the application program, such as load vector data or store vector data. The commands for transferring the data elements include a burst read command and a burst write command. A variable number of data elements may be transferred, according to the user's requirements. The system command bus is also capable of transmitting a packing ratio that indicates the number of data elements that fit in the width of the external bus. This allows the entire bandwidth of the external bus to be used during vector data transfers. The external bus also includes an address bus for transmitting the starting address, the length, and the stride of the vector data to be transferred. This allows an external agent to properly unpack the data elements on their correct boundary. Input and output validity signals provide an indication of the validity of the data elements transferred as well as to indicate when the transfer of the data elements is interrupted. A system clock signal is also included in the external bus to indicate the transfer rate of the data elements.

Dependencies are inferred from the claim text.