US 6,665,698 B1Granted

High speed incrementer/decrementer

AssigneeHewlett-Packard Development Company, L.P.

InventorsLi C Tsai, Daniel Krueger

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Abstract

A high speed incrementer/decrementer design is presented that computes the propagate, generate, and kill signals which are used to compute carries and sums from the incrementer inputs. By setting one input to “0” and the carry-in to “1”, the adder is used as an incrementer. In the design of the invention, a bit-wise decision is made whether to complement the input bit or not. The design also allows decrementing and supports both unsigned and 2's complement number representations.

Claims14

Dependent claims

A circuit which increments/decrements an n-bit input signal, comprising:

a multiplexer circuit which receives said n-bit input signal and a complement of said input signal, and outputs an n-bit output signal and overflow/underflow indicator which indicates whether said output signal is valid, said multiplexer receiving a select signal which selects on a bit-wise basis one or the other of said input signal bit and said complement input signal bit for output as the corresponding bit of said n-bit output signal;
a selection circuit which generates said select signal and, for each of said n bits of said input signal, selects one or the other of said input signal bit and said complement input signal bit for output as said corresponding output signal bit, said selection circuit comprising:
a plurality of group all-one evaluators, each corresponding to a mutually-exclusive grouping of successively significant bits of said input signal, and each determining and indicating via a corresponding group all-one evaluator output signal whether all of said bits in said corresponding grouping have a logical “1” value;
and
a plurality of partial all-one evaluators, each corresponding to one of said input signal bits and zero or more lower significant group all-one evaluators, and each determining and indicating, as said selection signal to said multiplexer corresponding to said corresponding partial all-one evaluator input signal bit, whether each input signal bit that comprises a lower significant bit than said corresponding partial all-one evaluators input signal bit that is also not included in one of said groupings of said lower significant group all-one evaluators has a logical “1” value and each of said corresponding lower significant group all-one evaluators indicate that all of said bits in said corresponding lower significant group all-one evaluator grouping have a logical “1” value, wherein each said lower significant group all-one evaluators comprises each of said plurality o group all-one evaluators that correspond to a mutually-exclusive grouping wherein all of said successively significant bits in said corresponding mutually-exclusive grouping comprises a lower significant bit than said corresponding partial all-one evaluator input signal bit;
wherein if an increment operating is performed, said complement input signal bit is selected if all lower significant input signal bits of said input signal bit have a logical “1” value and said input signal bit is selected if any of said lower significant input signal bits of said input signal bit have a logical “0” value.

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Dependencies are inferred from the claim text.

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Abstract

A circuit which increments/decrements an n-bit input signal, comprising:

a multiplexer circuit which receives said n-bit input signal and a complement of said input signal, and outputs an n-bit output signal and overflow/underflow indicator which indicates whether said output signal is valid, said multiplexer receiving a select signal which selects on a bit-wise basis one or the other of said input signal bit and said complement input signal bit for output as the corresponding bit of said n-bit output signal;
a selection circuit which generates said select signal and, for each of said n bits of said input signal, selects one or the other of said input signal bit and said complement input signal bit for output as said corresponding output signal bit, said selection circuit comprising:
a plurality of group all-one evaluators, each corresponding to a mutually-exclusive grouping of successively significant bits of said input signal, and each determining and indicating via a corresponding group all-one evaluator output signal whether all of said bits in said corresponding grouping have a logical “1” value;
and
a plurality of partial all-one evaluators, each corresponding to one of said input signal bits and zero or more lower significant group all-one evaluators, and each determining and indicating, as said selection signal to said multiplexer corresponding to said corresponding partial all-one evaluator input signal bit, whether each input signal bit that comprises a lower significant bit than said corresponding partial all-one evaluators input signal bit that is also not included in one of said groupings of said lower significant group all-one evaluators has a logical “1” value and each of said corresponding lower significant group all-one evaluators indicate that all of said bits in said corresponding lower significant group all-one evaluator grouping have a logical “1” value, wherein each said lower significant group all-one evaluators comprises each of said plurality o group all-one evaluators that correspond to a mutually-exclusive grouping wherein all of said successively significant bits in said corresponding mutually-exclusive grouping comprises a lower significant bit than said corresponding partial all-one evaluator input signal bit;
wherein if an increment operating is performed, said complement input signal bit is selected if all lower significant input signal bits of said input signal bit have a logical “1” value and said input signal bit is selected if any of said lower significant input signal bits of said input signal bit have a logical “0” value.

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