Delayed adaptive least-mean-square digital filter

A method for implementing a one-clock-cycle-per-tap delayed adaptive least-mean-square filter in a programmable digital signal processor, the filter acquiring a new data sample each frame of a time sequence of frames, the method comprising:

• reading a coefficient from a coefficient buffer;
• reading from a data buffer a first data sample corresponding to the coefficient;
• multiplying the coefficient and the first data sample and accumulating the product in a register to form an output of a finite impulse response (FIR) filter;
• updating the coefficient by adding to the coefficient the product of an error term, calculated during the frame immediately preceding the current frame, and a second data sample acquired during the frame immediately preceding the frame in which the first data sample was acquired by
• multiplying, during each clock cycle, a data sample and a corresponding coefficient, and
• accumulating the products to determine the FIR filter output;
• and
• writing the immediately preceding coefficient to the coefficient buffer.

A circuit architecture in a programmable digital signal processor for implementing a delayed adaptive least-mean-square filter in one clock cycle per tap, the filter acquiring a new data sample each frame of a time sequence of frames, the circuit architecture comprising:

• an error term buffer storing an error term calculated during a frame immediately preceding the current frame;
• a data buffer to hold data samples;
• a coefficient buffer to hold the current values of filter coefficients;
• wherein the coefficient buffer and the data buffer each comprise a random access memory accessible at least twice in one clock cycle;
• first and second multiply and accumulate circuits;
• and
• an arithmetic logic unit, wherein:
• the first multiply and accumulate circuit multiplies a data sample recalled from said data buffer and a corresponding coefficient recalled from said coefficient buffer to generate an output of a finite impulse response (FIR) filter;
• the second multiply and accumulate circuit multiplies the data sample recalled from said data buffer and an error term recalled from said error term buffer, calculated during the frame immediately preceding the current frame, to generate a first update term generated during the current clock cycle, and
• the arithmetic logic unit sums a second update term, generated during the clock cycle immediately preceding the current clock cycle by said second multiply and accumulate circuit, and the coefficient recalled from said coefficient buffer for updating the coefficient during the clock cycle immediately following the current clock cycle.