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US 6,665,627 B2Granted
Method and apparatus for evaluating and correcting the tester derating factor (TDF) in a test environment
AssigneeIntel Corporation
InventorsSunil K. Jain, Greg P. Chema
Life of this patent
Estimating the term…
Abstract
Tester derating factor (TDF) arrangements and methodologies providing improvements in semiconductor start-to-finish manufacturing arrangements, especially within DV testing and in the world of designing of devices and virtual simulation.
Claims27
A tester derating factor (TDF) arrangement, comprising:
- a design validation (DV) setup including a DV tester to obtain DV testing data for plurality of pins of a device under test (DUT);
- a second tester to obtain more accurate testing data for at least one selected pin of the DUT, at a position which is less electrically remote from the DUT than the DV tester;
- a TDF determination arrangement to determine a TDF for the at least one selected pin using at least one difference between the DV testing data and the more accurate testing data, for use to adjust DV testing data of ones of the plurality of pins which are analogous in type to the at least one selected pin, to TDF-adjusted DV data by applying the TDF thereto.
A design validation (DV) system having a tester derating factor (TDF) arrangement, comprising:
- a design validation (DV) setup including a DV tester to obtain DV testing data for plurality of pins of a device under test (DUT);
- a second tester to obtain more accurate testing data for at least one selected pin of the DUT, at a position which is less electrically remote from the DUT than the DV tester;
- a TDF determination arrangement to determine a TDF for the at least one selected pin using at least one difference between the DV testing data and the more accurate testing data, for use to adjust DV testing data of ones of the plurality of pins which are analogous in type to the at least one selected pin, to TDF-adjusted DV data by applying the TDF thereto.
A tester derating factor (TDF) method, comprising:
- using a design validation (DV) setup including a DV tester to obtain DV testing data for plurality of pins of a device under test (DUT);
- using a second tester to obtain more accurate testing data for at least one selected pin of the DUT, at a position which is less electrically remote from the DUT than the DV tester;
- using a TDF determination arrangement to determine a TDF for the at least one selected pin using at least one difference between the DV testing data and the more accurate testing data, for use to adjust DV testing data of ones of the plurality of pins which are analogous in type to the at least one selected pin, to TDF-adjusted DV data by applying the TDF thereto.
Tester derating factor (TDF) software provided on a tangible medium, said software comprising an arrangement capable of running operations of:
- accepting at least a portion of design validation (DV) testing data for plurality of pins of a device under test (DUT), as determined using a design validation (DV) setup including a DV tester;
- accepting more accurate testing data for at least one selected pin of the DUT, as was determined at a position which is less electrically remote from the DUT than the DV tester using a second tester;
- using a TDF determination arrangement to determine a TDF for the at least one selected pin using at least one difference between the DV testing data and the more accurate testing data, for use to adjust DV testing data of ones of the plurality of pins which are analogous in type to the at least one selected pin, to TDF-adjusted DV data by applying the TDF thereto.
Dependencies are inferred from the claim text.