Digital receive phase lock loop with phase-directed sample selection
Assignee3Com Corporation
InventorEric Stine
Life of this patent
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Abstract
PLL error margin is improved by a half clock of the internal PLL clock by resolving the ambiguity between the two samples nominally centered about the pulse center point. This is achieved by intelligently choosing between the two samples nearest the pulse center by exploiting information from the phase error. Specifically, the choice is made depending upon the sign of the phase error. The result is that the margin of error of the PLL is improved by a half clock period, since on the average the choice between each one of the two samples represents half of the total one-clock resolution limit of the system.
Claims30
A digital phase lock loop (PLL) having phase error-directed sample selection about a pulse center point, said PLL having an internal PLL clock and comprising:
- a data signal input at which an incoming data signal is received, said data signal comprising successive pulses having a characteristic pulse edge rate, said internal PLL clock having a clock rate about M times said pulse edge rate to define M successive samples of each one of said successive pulses;
- a state machine having an internal cyclic count of modulus M incremented in synchronism with said internal PLL clock, corresponding to M successive samples of each one of said successive pulses, said internal cyclic count including:
- (a) a predetermined center count value tending to coincide with center regions of said successive pulses, and
- (b) a predetermined edge count value offset from said center count value by approximately one half of one pulse width of said successive pulses and tending to coincide with edges of the successive pulses;
- sampling logic connected to receive said data signal and having a sampling control input connected to an output of said state machine, said sampling logic being capable of selecting a current one of said M successive samples whenever said internal count reaches the predetermined center count value;
- a phase error detector having one input for receiving said internal count from said state machine and an edge input responsive to receipt of said edges of said successive pulses, and producing a correction output signal corresponding to a phase difference between the time of occurrence of at least one of said successive edges and the time of occurrence of said edge count value of said internal count;
- said state machine further comprising a control input for advancing or retarding said internal count, said control input receiving at least a portion of said correction output signal;
- and
- a selective delay element connected between said data signal input and said sampling logic and having a select input connected to receive a sign bit of said correction output signal corresponding to the sign of said phase difference, said selective delay element capable of interposing a delay of one period of said internal PLL clock depending upon said sign bit, whereby to select between one of two samples near the center of a current pulse.
A method of synchronizing a digital circuit with the phase of an incoming data signal, said data signal comprising successive pulses having a characteristic pulse edge rate, said digital circuit having an internal PLL clock with a clock rate about M times said pulse edge rate to define M successive samples of each one of said successive pulses, said method comprising:
- a data signal input at which an incoming data signal is received,
- incrementing a state machine through an internal cyclic count of modulus M in synchronism with said internal PLL clock, corresponding to M successive samples of each one of said successive pulses, said internal cyclic count including:
- (a) a predetermined center count value tending to coincide with center regions of said successive pulses, and
- (b) a predetermined edge count value offset from said center count value by approximately one half of one pulse width of said successive pulses and tending to coincide with edges of the successive pulses;
- selecting a current one of said M successive samples whenever said internal count reaches the predetermined center count value;
- sensing receipt of said edges of said successive pulses, and producing a correction output signal corresponding to a phase difference between the time of occurrence of at least one of said successive edges and the time of occurrence of said edge count value of said internal count;
- advancing or retarding said internal count in accordance with said correction output signal;
- and
- outputting one of (a) said current one sample, (b) a sample immediately following said current one sample depending upon the state of a sign bit of a cumulative phase error register, whereby to select between one of two samples near the center of a current pulse.
A digital phase lock loop (PLL) having phase error-directed sample selection about a pulse center point, said PLL having an internal PLL clock and comprising:
- a state machine having an internal count cycle of modulus M incremented in synchronism with said internal PLL clock, corresponding to M successive samples of each one of successive pulses;
- sampling logic responsive to said state machine for sampling a current one of said pulses during one predetermined count of said internal count cycle;
- a phase error detector producing a correction output signal corresponding to a phase difference between the time of occurrence of at least one of successive edges and the time of occurrence of said one predetermined count;
- said state machine further comprising a control input for advancing or retarding said internal count, said control input receiving at least a portion of said correction output signal;
- and
- a selective delay element for delaying by one sample the arrival of successive samples at gate sampling logic and having a select input connected to receive a sign bit of said correction output signal corresponding to the sign of said phase difference, whereby to select between one of two samples coinciding with said one predetermined internal count.
Dependencies are inferred from the claim text.