Data transmitter with sequential serialization
AssigneeCypress Semiconductor Corporation
InventorMichael L. Duffy
Life of this patent
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Abstract
An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) a first control signal, (ii) a second control signal, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal. The second circuit may be configured to generate one or more intermediate data signals operating at a second speed in response to (i) the first control signal, (ii) the one or more first clock signals and (iii) the first data signal. The third circuit may be configured to generate an output data signal operating at a third speed in response to (i) the second control signal and (ii) the one or more intermediate data signals.
Claims18
An apparatus comprising:
- a first circuit configured to generate (i) one or more first control signals, (ii) one or more second control signals, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal;
- a first serialization element configured to generate one or more intermediate data signals operating at a second speed in response to (i) said one or more first control signals, (ii) said one or more first clock signals and (iii) said first data signal;
- and
- a second serialization element comprising a multiplexer configured to generate an output data signal operating at a third speed in response to (i) said one or more second control signals and (ii) said one or more intermediate data signals operating at a second speed.
A method for improving efficiency and precision of a data transmission device comprising the steps of:
- generating (i) one or more first control signals, (ii) one or more second control signals, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal and (ii) a reference clock signal;
- generating one or more intermediate data signals operating at a second speed using a first serialization element, in response to (i) said one or more first control signals, (ii) said one or more first clock signals and (iii) said first data signal;
- and
- generating an output data signal operating at a third speed using a second serialization element comprising a multiplexer, in response to (i) said one or more second control signals and (ii) said one or more intermediate data signals operating at a second speed.
An apparatus comprising:
- a first circuit configured to generate (i) one or more first control signals, (ii) one or more second control signals, (iii) one or more first clock signals and (iv) a first data signal operating at a first speed in response to (i) an input data signal, (ii) a reference clock signal and (iii) a feedback clock signal;
- a second circuit configured to generate one or more intermediate data signals operating at a second speed in response to (i) said one or more first control signals, (ii) said one or more first clock signals and (iii) said first data signal;
- and
- a third circuit configured to generate an output data signal operating at a third speed in response to (i) said one or more second control signals and (ii) said one or more intermediate data signals operating at a second speed, wherein said first circuit comprises a fractional rate phase lock loop (PLL) comprising (i) a phase frequency detector configured to generate a third and a fourth control signal in response to said reference clock signal and said feedback clock signal, (ii) a loop filter configured to generate a fifth control signal in response to said third control signal and said fourth control signal, and (iii) a VCO configured to generate said one or more first clock signals in response to said fifth control signal.
Dependencies are inferred from the claim text.