Digital data separator
AssigneeSTMicroelectronics S.r.l.
InventorLance Leslie Flake
Life of this patent
Estimating the term…
Abstract
A digital data separator that is capable of separating data signals and clock signals from an encoded data stream. The digital data separator includes a synchronizer to synchronize the encoded data stream with the system clock of the digital data separator. An up-counter counts the number of clock pulses between valid logic 1's in the encoded digital data stream. Combination logic compares the value of the up-counter with established threshold values to determine whether the data separator has received a valid logic 1. The combinatorial logic also reset the up-counter on determining that a valid logic 1 was received.
Claims19
A method for separating data signals from clock signals in an encoded data stream, comprising:
- receiving an encoded data stream and a system clock signal at a synchronizer wherein the synchronizer includes two single synchronizers each capable of receiving one of two enable signals so that one of the two single synchronizers is enabled;
- generating an edge detect signal based on the received encoded data stream and the received system clock signal;
- incrementing an up-counter for every system clock pulse;
- comparing a value in the counter to a threshold based on the generated edge detect signal, wherein the comparing includes determining whether the generated edge detect signal is valid based on the threshold;
- and
- when the comparing indicates the generated edge detect signal is valid, resetting the counter based on the comparison.
A computer program product comprising:
- a computer usable medium having computer readable code embodied therein for processing encoded data, the computer usable medium comprising:
- a synchronizing module configured to received an encoded data stream and a system clock signal, including two single synchronizers each capable of receiving one of two enable signals so that one of the two single synchronizers is enabled;
- an edge detecting module configured to generate an edge detect signal based on the received encoded data stream and the received system clock signal;
- an up-counting module configured to increment a counter for every system clock pulse;
- a comparison module configured to compare a value in the counter to a plurality of thresholds based on the generated edge detect signal;
- and
- a resetting module configured to reset the counter based on the comparison.
A disk drive system, comprising:
- a disk drive adapted to receive media, the media having data stored thereon;
- a read head coupled to disk drive capable of reading data from the media and generating an encoded data stream;
- a synchronizer for synchronizing the encoded data stream with a system clock and generating a next edge detect signal including a first toggle flip-flop that generates at least two enable signals, at least two single synchronizers each capable of receiving one of the at least two enable signals so that one of the at least two single synchronizers is enabled, and an OR gate coupled to outputs of the at least two single synchronizers for generating the valid edge detect and next edge detect signals;
- an up-counter for counting the system clock pulses and outputting a count signal, wherein the up-counter is reset in response to a reset signal;
- and
- combinatorial logic producing the reset signal to reset the up-counter upon receiving the next edge detect signal and determining whether the next edge detect signal is valid based on the count signal, whereby the combinatorial logic outputs a data enable signal for each valid determination.
A digital data separator for separating data signals from clock signals in an encoded data stream, comprising;
- a synchronizer for synchronizing the encoded data stream with a system clock and generating a next edge detect signal, wherein the synchronizer includes two single synchronizers each capable of receiving one of two enable signals so that one of the two single synchronizers is enabled;
- an up-counter for counting the system clock pulses and outputting a count signal, wherein the up-counter is reset in response to a reset signal;
- and
- combinatorial logic producing the reset signal to reset the up-counter upon receiving the next edge detect signal and determining whether the next edge detect signal is valid based on the count signal, whereby the combinatorial logic outputs a data enable signal for each valid determination.
Dependencies are inferred from the claim text.