Circuit and method for providing a digital data signal with pre-distortion

Abstract

In accordance with the present invention a digital data signal is given a pre-distortion by means of combining the amplitudes of the digital data signal and of at least one delayed version of the digital data signal. The delayed digital data signal is provided by a delay circuit having an adjustable time delay. A circuit for detecting the duration of a signal pattern in the digital data signal that is indicative of the duration of a repetitively occurring signal segment that determines the delay appropriate in view of the current data rate of the data signal, generates an adjustment signal for adjusting the time delay provided by the adjustable delay circuit. In this way it is possible to add a full bit or partial bit pre-distortion of any desired order to the digital data signal even if the data rate of the digital data signal is unknown at the time of manufacturing the circuit for providing pre-distortion or is allowed to vary, without there being a need for a bit rate synchronous clock.

Dependencies are inferred from the claim text.