Full duplex transceiver

The transceiver system capable of simplex, half-duplex, or full duplex operation, comprising:

• a variable Intermediate Frequency (IF) generator and post-processor;
• a user-interface;
• a transceiver, said transceiver further comprising:
• an embedded controller;
• a first interface between said embedded controller and said variable IF generator and post-processor;
• a distinct second interface between said variable IF generator and post-processor and said transceiver, said distinct second interface to transfer variable transmit (TX) IF signals from said variable IF generator and post-processor to said transceiver, and said distinct second interface to transfer said receive (RX) IF signals from said transceiver to said variable IF generator and post processor;
• a distinct third interface between said embedded controller and said external user-interface;
• at least one antenna interface;
• an up-conversion path to convert said variable TX IF signals to TX Radio Frequency (RF) signals, said up-conversion path further comprising at least one fixed Phase Locked Oscillator (PLO), a transmit (TX) IF filter, said TX IF filter input being said variable TX IF signals generated by said variable IF generator and post-processor, a TX mixer having a first input and a distinctive second input, said first input being said TX IF filter output, said second input being one of said at least one fixed PLO output, a TX band-pass filter (BPF) connected to said TX mixer output, a TX amplifier connected to said TX BPF output, said TX amplifier configurable for constant on, constant off, or request to send (RTS) control, said up-conversion path connecting said TX RF signals to one of said at least one antenna interface;
• a down-conversion path connected to one of said at least one antenna interface, said down-conversion path to convert received (RX) RF signals to said RX IF signals, said down-conversion path further comprising said at least one fixed PLO, a receive (RX) BPF, said RX BPF input being said RX RF signals, a RX amplifier connected to said RX BPF output, a RX mixer having a first input and a distinctive second input, said first input being said RX amplifier output, said second input being one of said at least one fixed PLO output, a RX IF Filter connected to said RX mixer output, and a RX IF amplifier connected to said RX IF Filter output;
• a distinct fourth interface between said embedded controller and said transmit (TX) band-pass filter (BPF);
• a distinct fifth interface between said embedded controller and said receive (RX) BPF;
• a distinct sixth interface between said embedded controller and said TX amplifier;
• a distinct seventh interface between said embedded controller and an internal diplexer, said internal diplexer further comprising an internal diplexer TX terminal, an internal diplexer RX terminal, and an internal diplexer common terminal;
• an external diplexer interface, said external diplexer interface further comprising an external diplexer interface TX terminal, an external diplexer interface RX terminal, and an external diplexer common terminal;
• an internal oscillator reference to drive said at least one PLO;
• an external oscillator reference interface to allow said at least one PLO to be driven by an external oscillator;
• and,
• a distinct eighth interface between said embedded controller and said internal oscillator.