Synchronous mirror delay with reduced delay line taps

#The invention relates to integrated circuits, and more particularly, to synchronous mirror delay circuits with delay, line taps for double data rate (DDR) synchronous dynamic random access memory (SDRAM) devices.

#Memory access speed and the resulting data transfer bandwidth has been a typical bottleneck in computer systems and other digital applications. A newer type of dynamic random access memory (DRAM), known as a synchronous DRAM or SDRAM, has been developed to provide faster operation and improve memory access times. SDRAMs are designed to operate synchronously with the system clock with input and output data synchronized to an active edge of the system clock which is driving the processor accessing the SDRAM.

#Although SDRAMs have overcome some of the timing disadvantages of other memory devices memory, access is still a limiting factor, and there is a need for still faster memory devices. With this in mind, double data rate (DDR) SDRAMs were developed to allow data transfers on both the rising and falling edges of the system data clock, providing twice the operating speed of the conventional SDRAM. Thus, DDR SDRAM provides up to twice as much data bandwidth as the conventional SDRAM for a given data clock. In addition, as with SDRAM, DDR SDRAMs are also capable of providing bursts of data at a high-speed data rate.

#FIG. 1 is a wave diagram of a DDR SDRAM memory transfer showing the system clock signal, data signal (DQ), and DQS strobe.

#FIG. 2 is a diagram of a prior art DLL for an integrated circuit.

#FIG. 3 is a diagram of a DDR SDRAM memory data interface circuit showing DRAM core, data latch, clock recovery circuit, and DQS output.

#In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.

#FIG. 3 shows a generalized data interface of a DDR SDRAM memory, including a DRAM core 300, a data latch 302, and a generalized clock recovery and skew adjustment circuit 304. In operation, an external data clock is received through the clock input buffer 306. The external data clock is replicated and adjusted for skew by the clock recovery and skew adjustment circuit 304 and output as an internal clock signal 308. The internal clock signal 308 is utilized to trigger the data latch 302 on both the rising and falling edge of the clock, outputting data through buffer 310 onto the data bus. The internal clock signal is also utilized to drive the DQS strobe through buffer 312.

#FIG. 4 shows an example of a prior art SMD circuit which consists of a clock input buffer 410, a data path model (DPM) 400, forward delay line (FDL) 402, an SMD control circuit 404, a backward delay line (BDL) 406, and a clock driver circuit 408. The FDL 402 and BDL 406 are comprised of delay elements (not shown) that have the same unit delay. The input buffer 410 and clock driver 408 adds an additional internal delay for the SMD circuit of din for the input buffer 410 and delay of ddp for the clock driver circuit 408 to the circuit that is compensated for by the DPM 400.