US 6,665,231 B2 · Semiconductor device having pipelined dynamic memory

Abstract

A dynamic memory requires refreshing to retain data in its memory cells. This may cause access to the dynamic memory for purposes other than refreshing (external access) and access to it for refreshing to compete with each other, resulting in a performance deterioration. According to this invention, a pipelined dynamic memory (PDRAM) is used, and the pipeline frequency (CLK) of the pipelined dynamic memory is made higher than the frequency (CLK1) of external access, and access required for refreshing is made to an unoccupied slot (a timing when any external access request is never issued) in the pipeline of the pipelined dynamic memory. This makes refreshing of the internal dynamic memory an internal operation, which eliminates the need to take refreshing into consideration at the time external access is made, leading to improvement in operating ease and speed.

Claims15

Dependent claims

A semiconductor device supplied with a first clock and a second clock having a lower frequency than said first clock, and comprising:

a memory circuit including a plurality of dynamic memory cells provided at intersections of a bit line and a plurality of word lines, a row decoder coupled to said plurality of word lines, a row address latch circuit operative to latch read and write row addresses at transition points of the first clock and to supply the addresses to said row decoder,
wherein data is read from said dynamic memory cells by destructive readout, and
wherein said row address latch circuit includes a write delay circuit operative to delay the supply of write row addresses, but not read row addresses, to said row decoder by at least a predetermined number of cycles of said first clock.

Dependencies are inferred from the claim text.

Semiconductor device having pipelined dynamic memory

Life of this patent

Semiconductor device having pipelined dynamic memory

Life of this patent

Abstract

Claims15