Programmable delay compensation circuit
AssigneeDenali Software, Inc.
InventorsSteven Shrader, Art Gmurowski, Samitinjoy Pal, Michael McKeon
Life of this patent
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Abstract
Circuitry for programming the amount of delay applied to an input signal, the circuitry performing the method of determining the number of delay elements required to capture a clock cycle, receiving a programmable delay value and calculating the number of delay elements required to delay a clock signal by the received delay value and delaying the clock signal by the number of delay elements required to delay the clock signal by the programmable delay value.
Claims21
Circuitry for delaying an input signal according to a programmable delay value, comprising:
- clock capturing circuitry for determining a number of delay elements needed to capture a clock cycle of a clock signal with the same frequency as the input signal;
- delay calculation circuitry for:
- receiving the number of delay elements needed to capture the clock cycle from the clock capturing circuitry;
- receiving the programmable delay value;
- and
- calculating a number of delay elements needed to delay the input signal by the programmable delay value;
- and
- delay circuitry comprising:
- an input for receiving the input signal;
- a select input for receiving the number of delay elements needed to delay the input signal by the programmable delay value from the delay calculation circuitry;
- and
- a chain of delay elements, wherein the number of delay elements that the input signal is passed through is determined by the select input.
A method for delaying an input signal by a programmable delay value, comprising:
- determining a number of delay elements needed to capture a clock cycle of a clock signal with the same frequency as the input signal;
- receiving a programmable delay value;
- calculating a number of delay elements required to delay the input signal by the programmable delay value;
- and
- delaying the input signal by the number of delay elements required to delay the input signal by the programmable delay value.
A method for generating a write data strobe for a write operation to a DDR memory, comprising:
- generating a plurality of clock signals that have the same frequency as a master clock in the DDR memory, each of the plurality of clock signals being delayed by a different amount;
- receiving a programmable input;
- selecting one of the plurality of clock signals as the write data strobe based on the programmable input;
- and
- outputting the write data strobe.
Apparatus for delaying an input signal according to a programmable delay value, comprising:
- means for determining a number of delay elements needed to capture a clock cycle of a clock signal with the same frequency as the input signal;
- means for calculating the number of delay elements required to delay the input signal by a programmable delay value;
- and
- means for delaying the input signal by the number of delay elements required to delay the input signal by the programmable delay value.
Circuitry for delaying a read data strobe received from a dynamic random access memory (DRAM) during a read operation, comprising:
- delay calculation circuitry for receiving a programmable delay value and calculating a number of delay elements the read data strobe needs to be passed through to delay the read data strobe by the programmable delay value;
- and
- delay circuitry comprising:
- an input for receiving the read data strobe;
- and
- a chain of delay elements for delaying the read data strobe by the number of delay elements calculated in the delay calculation circuitry.
An apparatus for delaying a read data strobe received from a dynamic random access memory (DRAM), comprising:
- an input for receiving the read data strobe;
- and
- delay circuitry for delaying the read data strobe comprised of a plurality of delay elements, a subset of the plurality of delay elements used to delay the read data strobe by a programmable delay input.
Dependencies are inferred from the claim text.