Semiconductor memory device row decoder structures having reduced layout area, and methods of operating the same

A local row decoder structure of a nonvolatile semiconductor memory device to erase memory cells coupled to a single bitline, comprising:

• a plurality of local level converters, at least one of the local level converters including
• a PMOS transistor having a source for receiving a high voltage, a gate for receiving a bias voltage, and a drain,
• a first NMOS transistor having a drain coupled to the drain of the PMOS transistor, a gate for receiving a sector select signal, and a source, and
• a second NMOS transistor having a drain coupled to a source of the first NMOS transistor and a gate coupled to a global word line;
• and
• at least one word line driver coupled to each local level converter to erase at least one of the memory cells.

A semiconductor memory device for programming and erasing memory cells, comprising:

• sectors including a plurality of memory cell transistors that are connected to corresponding word lines at their gates, and connected to corresponding bit lines at their drains;
• global row decoders for decoding a first portion of address signals to thereby select at least one of the global word lines;
• partial decoders arranged in each of the sectors to decode a second portion of the address signals to thereby select at least one of partial word lines;
• local row decoders coupled with the global word lines for receiving a drive voltage of word line through the partial word lines to thereby enable at least one of the word lines wherein one local row decoders includes:
• a PMOS transistor having a source for receiving a high voltage and a gate for receiving a bias voltage from a bias driver,
• a first NMOS transistor having a drain coupled to a drain of the PMOS transistor and a gate for receiving the sector select signal, and
• a second NMOS transistor having a drain coupled to a source of the first NMOS transistor and a gate coupled to one of the global word lines;
• high voltage drivers for generating a high voltage to thereby input it to the local row decoders in response to a sector address signal;
• erase voltage drivers for generating an erase voltage to thereby input it to the local row decoders in response to a sector address signal;
• sector selectors for generating a sector select signal to input it to the local row decoders in response to the sector address signal;
• and
• bias drivers for generating a bias voltage to apply it to the local row decoders in response to the sector address signal.

An electrically programmable and erasable semiconductor memory, comprising:

• sectors comprising a plurality of word lines, a plurality bit lines and a plurality of memory cells;
• global row decoders including a logic part for receiving a decoding signal generated in response to an external address signal and for selecting a selected global word line, the global row decoder receiving an output of the logic part as an input, the global row decoder connected between a first power voltage terminal and a second power voltage terminal to output the first or second power voltage to a global word line;
• partial row decoders receiving an address of the global row decoder and a decoding signal generated in response to an external address signal, the partial decoder outputting a third power voltage to a selected partial word line;
• a sector select driver receiving a decoding signal and a control signal generated by the external address signal to output the selected sector signal;
• a bias driver receiving a decoding signal generated by the external address signal, the bias driver connected to between a fourth power voltage and a fifth power voltage terminal to output a fourth voltage and fifth voltage as a bias voltage;
• a high voltage driver receiving the decoding signal and a control signal generated in an internal, the high voltage driver connected between a sixth power voltage and a seventh power voltage to selectively output a sixth power voltage and a seventh power voltage;
• an erase voltage driver receiving the decoding signal and an internal control signal, the erase voltage driver connected between a eighth power voltage and a ninth power voltage to selectively output a eighth power voltage and a ninth power voltage;
• and
• a local row decoder receiving the sector select signal, bias voltage, high voltage, erase voltage, partial word line voltage, and global word line voltage to select one word line.

A method for driving a word line of an electrically programmable and erasable semiconductor memory device having a local level converter, and a word line driver coupled to the local level converter and to the word line, the method comprising:

• biasing the local level converter;
• applying a voltage from an output of the biased local level converter to the word line driver;
• and
• concurrently applying a voltage from a global word line to the word line driver to drive the word line.