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US 6,665,227 B2Granted
Method and apparatus for reducing average power in RAMs by dynamically changing the bias on PFETs contained in memory cells
AssigneeHewlett-Packard Development Company, L.P.
InventorEric S Fetzer
Life of this patent
Estimating the term…
Abstract
A circuit for reducing power in SRAMS and DRAMS is implemented by dynamically controlling a voltage applied to Nwells containing PFETs used in memory cells. When a memory cell is in standby, the voltage applied to Nwells containing PFETs is increased in order to reduce leakage current. When a memory cell is being written, read, or refreshed, the voltage applied to Nwells containing PFETs is reduced in order to allow the memory cell to switch more quickly.
Claims40
A circuit for reducing power in SRAM memory cells comprising:
- at least one contiguous Nwell region wherein said Nwell region contains at least two PFET transistors from said SRAM memory cells;
- at least one electrical contact to each of said Nwell regions;
- a first variable voltage source electrically connected to said contacts of said Nwell regions;
- a second variable voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in SRAM memory cells comprising:
- at least one contiguous Nwell region wherein said Nwell region contains at least two PFET transistors from said SRAM memory cells;
- at least one electrical contact to each of said Nwell regions;
- a variable voltage source electrically connected to said contacts of said Nwell regions;
- a fixed voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in SRAM memory cells comprising:
- at least one contiguous Nwell region wherein said Nwell region contains at least two PFET transistors from said SRAM memory cells;
- at least one electrical contact to each of said Nwell regions;
- a fixed voltage source electrically connected to said contacts of said Nwell regions;
- a variable voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in SRAM memory cells comprising:
- one individual contiguous Nwell region for each wordline contained in said SRAM memory cells wherein said Nwell region contains all PFET transistors on said wordline;
- at least one electrical contact to each of said Nwell regions;
- a first variable voltage source electrically connected to said contacts of said Nwell regions;
- a second variable voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in SRAM memory cells comprising:
- one individual contiguous Nwell region for each wordline contained in said SRAM memory cells wherein said Nwell region contains all PFET transistors on said wordline;
- at least one electrical contact to each of said Nwell regions;
- a variable voltage source electrically connected to said contacts of said Nwell regions;
- a fixed voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in SRAM memory cells comprising:
- one individual contiguous Nwell region for each wordline contained in said SRAM memory cells wherein said Nwell region contains all PFET transistors on said wordline;
- at least one electrical contact to each of said Nwell regions;
- a fixed voltage source electrically connected to said contacts of said Nwell regions;
- a variable voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A method for reducing power in SRAM memory cells comprising:
- forming at least one contiguous Nwell region wherein said Nwell region contains at least two PFET transistors from said SRAM memory cells;
- forming at least one electrical contact to each of said Nwell regions;
- electrically connecting a first variable voltage source to said contacts of said Nwell regions;
- electrically connecting a second variable voltage source to positive electrical connections of said memory cells;
- adjusting said first and second variable voltage sources such that the voltage applied to said memory cells minimizes leakage current in said SRAM memory cells.
2 more elements
A method for reducing power in SRAM memory cells comprising:
- forming one individual contiguous Nwell region for each wordline contained in said SRAM memory cells wherein said Nwell region contains all PFET transistors on said wordline;
- forming at least one electrical contact to each of said Nwell regions;
- electrically connecting a first variable voltage source to said contacts of said Nwell regions;
- electrically connecting a second variable voltage source to positive electrical connections of said memory cells;
- adjusting said first and second variable voltage sources such that the voltage applied to said memory cells minimizes leakage current in said SRAM memory cells.
2 more elements
A circuit for reducing power in DRAM memory cells comprising:
- at least one contiguous Nwell region wherein said Nwell region contains at least one PFET transistors from said DRAM memory cells;
- at least one electrical contact to each of said Nwell regions;
- a first variable voltage source electrically connected to said contacts of said Nwell regions;
- a second variable voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in DRAM memory cells comprising:
- at least one contiguous Nwell region wherein said Nwell region contains at least one PFET transistors from said DRAM memory cells;
- at least one electrical contact to each of said Nwell regions;
- a variable voltage source electrically connected to said contacts of said Nwell regions;
- a fixed voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in DRAM memory cells comprising:
- at least one contiguous Nwell region wherein said Nwell region contains at least one PFET transistors from said DRAM memory cells;
- at least one electrical contact to each of said Nwell regions;
- a fixed voltage source electrically connected to said contacts of said Nwell regions;
- a variable voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in DRAM memory cells comprising:
- one individual contiguous Nwell region for each wordline contained in said DRAM memory cells wherein said Nwell region contains all PFET transistors on said wordline;
- at least one electrical contact to each of said Nwell regions;
- a first variable voltage source electrically connected to said contacts of said Nwell regions;
- a second variable voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in DRAM memory cells comprising:
- one individual contiguous Nwell region for each wordline contained in said DRAM memory cells wherein said Nwell region contains all PFET transistors on said wordline;
- at least one electrical contact to each of said Nwell regions;
- a variable voltage source electrically connected to said contacts of said Nwell regions;
- a fixed voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A circuit for reducing power in DRAM memory cells comprising:
- one individual contiguous Nwell region for each wordline contained in said DRAM memory cells wherein said Nwell region contains all PFET transistors on said wordline;
- at least one electrical contact to each of said Nwell regions;
- a fixed voltage source electrically connected to said contacts of said Nwell regions;
- a variable voltage source electrically connected to positive electrical connections of said memory cells.
1 more element
A method for reducing power in DRAM memory cells comprising:
- forming at least one contiguous Nwell region wherein said Nwell region contains at least one PFET transistors from said DRAM memory cells;
- forming at least one electrical contact to each of said Nwell regions;
- electrically connecting a first variable voltage source to said contacts of said Nwell regions;
- electrically connecting a second variable voltage source to positive electrical connections of said memory cells;
- adjusting said first and second variable voltage sources such that the voltage applied to said memory cells minimizes leakage current in said DRAM memory cells.
2 more elements
A method for reducing power in DRAM memory cells comprising:
- forming one individual contiguous Nwell region for each wordline contained in said DRAM memory cells wherein said Nwell region contains all PFET transistors on said wordline;
- forming at least one electrical contact to each of said Nwell regions;
- electrically connecting a first variable voltage source to said contacts of said Nwell regions;
- electrically connecting a second variable voltage source to positive electrical connections of said memory cells;
- adjusting said first and second variable voltage sources such that the voltage applied to said memory cells minimizes leakage current in said DRAM memory cells.
2 more elements
Dependencies are inferred from the claim text.