Partial refresh for synchronous dynamic random access memory (SDRAM) circuits
AssigneeInfineon Technologies AG
InventorsGunther Lehmann, Manfred Menke
Life of this patent
Estimating the term…
Abstract
A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of portions of the DRAM 300 to be refreshed, saving power and time over DRAMs that refresh the entire memory. The counter 345 may be programmed with a wordline address at the beginning of a block of memory and subsequent refresh operations automatically increment or decrement the value in the counter. Additionally, blocks of the memory not being refreshed can be accessed (written or read), improving the utilization of the memory device.
Claims33
A semiconductor memory device comprising:
- a memory comprising a plurality of memory storage cells;
- a command interface coupled to the memory, the command interface containing circuitry to decode commands provided to the device by a user and provide the decoded commands to control the operation of the device;
- a refresh circuit coupled to the memory and the command interface, the refresh circuit to provide an address of a portion of the memory to be refreshed, the refresh circuit comprising:
- a programmable counter having a first input coupled to the command interface and a second input coupled to an address bus, the programmable counter containing circuitry to store an address provided on the address bus and to provide the stored address on an output of the refresh circuit;
- and
- a selection circuit having an input coupled to the command interface and an output coupled to the second input of the programmable counter, the selection circuit having circuitry to pass the address provided by the address bus to the programmable counter based on a command from the command interface.
A dynamic random access memory (DRAM) device comprising:
- a memory containing a plurality of memory cells to store binary data, each memory cell including a transistor coupled in series with a capacitor;
- a command interface coupled to the memory, the command interface containing circuitry to decode commands provided to the device;
- a refresh circuit coupled to the memory and the command interface, the refresh circuit containing circuitry to provide an address of a portion of the memory to be refreshed;
- wherein the command interface decodes a single external refresh command into first and second internal commands:
- the first internal command being a bank activate (RAS) command, activating a portion of the memory corresponding to an address received from an external address bus;
- and
- the second internal command being a precharge (PRE) command to the portion of memory refreshed by the RAS command.
A method for refreshing a contiguous block of memory comprising:
- (a) specifying an address corresponding to a start of the contiguous block of memory;
- (b) issuing a first memory refresh command;
- (c) issuing a second memory refresh command;
- and
- (d) repeating step (c) without repeating step (a) until the contiguous block of memory is refreshed.
A memory device comprising:
- an array of memory cells;
- a first address latch coupled to an address bus;
- a second address latch with a first input coupled to an output of the first address latch, the second address latch including a first output coupled to the array of memory cells;
- a counter with an address input and an address output;
- a first select circuit having an input coupled to a second output of the second address latch and an output coupled to the address input of the counter;
- and
- a second select circuit with an input coupled to the address output of the counter and an output coupled to a second input of the second address latch.
A method of refreshing a contiguous block of memory cells in a memory device, the method comprising:
- receiving an external address indicating an end-point of the contiguous block of memory cells, the external address being received from a source external to the memory device synchronously with a clock signal;
- storing the address in a programmable counter,
- refreshing memory cells corresponding to the address stored in the programmable counter;
- receiving an auto refresh command from a source external to the memory device synchronously with a clock signal;
- modifying contents of the programmable counter in response to the auto refresh command to obtain a modified address of memory cells;
- refreshing memory cells corresponding to the modified address;
- and
- repeating the steps of receiving an auto refresh command, modifying contents of the programmable counter, and refreshing memory cells corresponding to the modified address until all memory cells in the contiguous block are refreshed.
Dependencies are inferred from the claim text.