Memory device and method having data path with multiple prefetch I/O configurations
AssigneeMicron Technology, Inc.
InventorsBrent Keeth, Brian Johnson, Troy A. Manning
Life of this patent
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Abstract
A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
Claims11
A method of coupling data from a memory array to data bus terminals, comprising:
- transferring from an array 2N bits of data in a first operating mode and N bits of data in a second operating mode, the data being transferred through X sets of buses each having a width of M bits;
- converting the transferred parallel data to serial data;
- and
- applying respective bursts of serial data to 2Y data bus terminals in a first mode and Y data bus terminals in a second mode, each of the bursts containing N/Y bits.
Dependencies are inferred from the claim text.