US 6,665,221 B2Granted

Multiple bit line column redundancy with primary local and global bit lines and redundant local and global bit lines

AssigneeMicron Technology, Inc.

InventorsEbrahim Abedifard, Frankie F. Roohparvar

Life of this patent

Estimating the term…

Loading patent…

Abstract

Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Such memory devices include blocks of memory cells arranged in columns with each column of memory cells coupled to a local bit line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. A defect in one column of memory cells results in replacement of four or more columns of memory cells.

Claims16

Dependent claims

An electronic system, comprising:

a processor;
and
a memory device coupled to the processor, wherein the memory device comprises:
a memory array having at least one memory bank, each memory bank having at least one memory sector, and each memory sector having at least one memory block, wherein each memory block has columns of addressable memory cells, each column of memory cells being coupled to a local bit line;
at least one primary grouping of memory cells in a first memory sector, the at least one primary grouping of memory cells comprising a primary sensing device coupled to a first primary global bit line and a second primary global bit line, wherein each primary global bit line is coupled to at least two local bit lines of each memory block of the first memory sector;
at least one redundant grouping of memory cells in the first memory sector, the at least one redundant grouping of memory cells comprising a redundant sensing device coupled to a first redundant global bit line and a second redundant global bit line, wherein each redundant global bit line is coupled to at least two local bit lines of each memory block of the first memory sector;
a comparator coupled to the at least one primary grouping of memory cells and the at least one redundant grouping of memory cells for selectively accessing one of the redundant groupings of memory cells when an address applied to the memory array corresponds to a memory cell in a known defective primary grouping of memory cells in the first memory sector;
address inputs coupled between the memory array and the processor;
and
data inputs/outputs coupled between the memory array and the processor.

7 more elements

An electronic system, comprising:

a processor;
and
a memory device coupled to the processor, wherein the memory device comprises:
an address register for receiving an address from the processor;
a row decoder circuit;
a column decoder circuit;
and
a memory array coupled to the row decoder circuit and the column decoder circuit for accessing the memory array in response to the received address, the memory array comprising:
a first memory block having columns of memory cells coupled to a plurality of first local bit lines;
a second memory block having columns of memory cells coupled to a plurality of second local bit lines;
at least one primary grouping of memory cells, comprising a primary sensing device coupled to a first primary global bit line and a second primary global bit line, wherein each primary global bit line is coupled to at least two primary local bit lines from the plurality of first local bit lines and at least two primary local bit lines from the plurality of second local bit lines through selective coupling devices;
and
at least one redundant grouping of memory cells, comprising a redundant sensing device coupled to a first redundant global bit line and a second redundant global bit line, wherein each redundant global bit line is coupled to at least two redundant local bit lines from the plurality of first local bit lines and at least two redundant local bit lines from the plurality of second local bit lines through selective coupling devices.

10 more elements

An electronic system, comprising:

a processor;
and
a synchronous flash memory device coupled to the processor, wherein the synchronous flash memory device comprises:
a memory array having non-volatile flash memory cells;
and
a command execution logic coupled to the memory array for receiving at least a system clock input signal and for generating commands to control operations performed on the memory array, wherein the commands are synchronized to the system clock input signal;
wherein the memory array further comprises:
a first memory block having columns of the non-volatile flash memory cells coupled to a plurality of first local bit lines;
a second memory block having columns of the non-volatile flash memory cells coupled to a plurality of second local bit lines;
at least one primary grouping of memory cells, comprising a primary sensing device coupled to a first primary global bit line and a second primary global bit line, wherein each primary global bit line is coupled to at least two primary local bit lines from the plurality of first local bit lines and at least two primary local bit lines from the plurality of second local bit lines through selective coupling devices;
and
at least one redundant grouping of memory cells, comprising a redundant sensing device coupled to a first redundant global bit line and a second redundant global bit line, wherein each redundant global bit line is coupled to at least two redundant local bit lines from the plurality of first local bit lines and at least two redundant local bit lines from the plurality of second local bit lines through selective coupling devices.

9 more elements

An electronic system, comprising:

a processor;
and
a synchronous flash memory device coupled to the processor, wherein the synchronous flash memory device comprises:
a memory array having non-volatile flash memory cells;
and
a command execution logic coupled to the memory array for receiving at least a system clock input signal and for generating commands to control operations performed on the memory array, wherein the commands are synchronized to the system clock input signal;
wherein the memory array further comprises:
at least one memory block having columns of the non-volatile flash memory cells, each column of the non-volatile flash memory cells being coupled to a local bit line;
at least one primary grouping of memory cells, comprising a primary sensing device coupled to a first primary global bit line and a second primary global bit line, wherein each primary global bit line is coupled to at least two local bit lines of each memory block;
and
at least one redundant grouping of memory cells, comprising a redundant sensing device coupled to a first redundant global bit line and a second redundant global bit line, wherein each redundant global bit line is coupled to at least two local bit lines of each memory block.

8 more elements

Dependencies are inferred from the claim text.