Self calibrating register for source synchronous clocking systems
AssigneeAgilent Technologies, Inc.
InventorsPeter J. Meier, Gerald L Esch, Jr.
Life of this patent
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Abstract
A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.
Claims9
A register for storing data, which comprises:
- a delay circuit, wherein the delay circuit is configured to receive a data signal, and to transmit a delayed data signal and wherein the delayed data signal is the data signal delayed by a first delay time;
- and
- a register cell, wherein the register cell is configured to receive the delayed data signal transmitted by the delay circuit and a delayed clock signal, wherein the delayed clock signal is obtained by delaying a reference clock signal by a second delay time, and wherein the register cell is configured to store the delayed data signal upon enablement by the delayed clock signal.
Dependencies are inferred from the claim text.