Memory cell read device with a precharge amplifier and associated methods
AssigneeSTMicroelectronics S.r.l.
InventorsSigrid Thomas, Leïla Aitouarab
Life of this patent
Estimating the term…
Abstract
In a device for reading memory cells, a precharging circuit is connected to a memory cell to be read and to a reference cell associated with the memory cell to be read. The precharging circuit precharges the output of the differential amplifier to a predetermined voltage level. The reading device further includes an inverter having a high threshold and a low threshold connected to the output of the differential amplifier. The predetermined voltage level corresponds to an intermediate level between the high and low thresholds.
Claims23
A memory cell reading device comprising:
- a differential amplifier having a first input connected to a memory cell to be read and a second input connected to a reference cell associated with the memory cell to be read;
- and
- a precharging circuit connected to an output of said differential amplifier for precharging the output to a predetermined voltage level during a reading phase of the memory cell, said precharging circuit comprising
- an upper arm comprising a PMOS transistor configured as a diode, and an activation PMOS transistor connected to said PMOS transistor and being controlled by a first precharging signal, and
- a lower arm connected to said upper arm and comprising an NMOS transistor configured as a diode, and an activation NMOS transistor connected to said NMOS transistor and being controlled by a second precharging signal.
A memory cell reading device comprising:
- a differential amplifier having a first input connected to a memory cell to be read and a second input connected to a reference cell associated with the memory cell to be read;
- a balancing circuit connected between the first and second inputs of said differential amplifier;
- and
- a precharging circuit connected to an output of said differential amplifier for precharging the output to a predetermined voltage level during a reading phase of the memory cell, said precharging circuit comprising
- an upper arm comprising a PMOS transistor configured as a diode, and an activation PMOS transistor connected to said PMOS transistor and being controlled by a first precharging signal, and
- a lower arm connected to said upper arm and comprising a an NMOS transistor configured as a diode, and an activation NMOS transistor connected to said NMOS transistor and being controlled by a second precharging signal.
A memory comprising:
- a plurality of memory cells;
- at least one reference cell;
- and
- a memory cell reading device connected to said plurality of memory cells and to said at least one reference cell, said memory cell reading device comprising
- at least one differential amplifier having a first input connected to a memory cell to be read and a second input connected to said at least one reference cell, and
- at least one precharging circuit connected to an output of said at least one differential amplifier for precharging the output to a predetermined voltage level during a reading phase of the selected memory cell, said at least one precharging circuit comprising
- an upper arm comprising a PMOS transistor configured as a diode, and an activation PMOS transistor connected to said PMOS transistor and being controlled by a first precharging signal, and
- a lower arm connected to said upper arm and comprising an NMOS transistor configured as a diode, and an activation NMOS transistor connected to said NMOS transistor and being controlled by a second precharging signal.
A method for reading a memory cell having associated therewith a reference cell, and a differential amplifier having a first input connected to the memory cell and a second input connected to the reference cell, the method comprising:
- precharging an output of the differential amplifier to a predetermined voltage level during a reading phase of the memory cell using a precharging circuit connected to the output of the differential amplifier, the precharging circuit comprising an upper arm comprising a PMOS transistor configured as a diode, and an activation PMOS transistor connected to the PMOS transistor and being controlled by a first precharging signal, and a lower arm connected to the upper arm and comprising an NMOS transistor configured as a diode, and an activation NMQS transistor connected to the NMOS transistor and being controlled by a second precharging signal;
- balancing the first and second inputs of the differential amplifier during a precharging phase using a balancing circuit connected between the first and second inputs of the differential amplifier;
- and
- deactivating the precharging circuit after the first and second inputs have been balanced and the balancing circuit has been deactivated.
Dependencies are inferred from the claim text.