Sense amplifier circuit and method for nonvolatile memory devices
AssigneeSTMicroelectronics S.r.l.
InventorsOron Michael, Ilan Sever
Life of this patent
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Abstract
A sense amplifier circuit and method are disclosed for nonvolatile memory devices, such as flash memory devices. The sense amplifier circuit includes a current source that is configurable to source any of at least two nonzero current levels in the sense amplifier circuit. The sense amplifier circuit is controlled by control circuitry in the nonvolatile memory device so that each sense amplifier circuit sources a first current level during the precharge cycle of a memory read operation, and a second current level, greater than the first current level, during the memory cell sense operation. In this way, the sense amplifier circuit consumes less power during the memory read operation without an appreciable loss in performance.
Claims23
A sense amplifier circuit for a memory device, comprising:
- a pair of input transistors, each input transistor having a first conduction terminal coupled to the first conduction terminal of the other input transistor, a control terminal and a second conduction terminal, an output of the sense amplifier circuit being coupled to the second conduction terminal of one of the input transistors;
- a pair of load elements, each load element being coupled between the second conduction terminal of a distinct one of the input transistors and a first reference voltage source;
- and
- a current source coupled between the first conduction terminals of the input transistors and a second reference voltage source, and configurable to draw any of at least two non-zero current levels through the current source.
A method for operating a sense amplifier circuit within a memory device during a memory access operation, comprising:
- applying one or more input signals to the sense amplifier circuit;
- generating, during a first time period of the memory access operation, at least one output signal having a voltage representative of the one or more input signals, the at least one output signal being generated while the sense amplifier dissipates a first non-zero current level;
- and
- generating, during a second time period of the memory access operation following the first time period, the at least one output signal while the sense amplifier dissipates a second non-zero current level greater than the first non-zero current level.
A sense amplifier circuit for an integrated circuit having a plurality of memory cells for storing information, the sense amplifier circuit comprising circuitry for receiving at least one data input signal and at least one control input signal, for selectively providing an output signal having a value representative of the at least one data input signal, the sense amplifier being selectively controlled based upon the at least one control input signal to dissipate current at a first non-zero current level and at a second non-zero current level different from the first non-zero current level.
Dependencies are inferred from the claim text.