Memory arrangement with selectable memory sectors
AssigneeInfineon Technologies AG
InventorThomas Kern
Life of this patent
Estimating the term…
Abstract
In order to achieve a maximally space-saving configuration of a matricial memory arrangement (1), for example in the form of a non-volatile flash memory, which comprises a plurality of memory cells (3) grouped into memory sectors (2), it is proposed to use regular memory cells (4) of this memory arrangement (1) as sector switches for selecting/activating the respective memory sector (2). In order to avoid the effect of high voltages on the threshold voltage of the memory cells (4) configured as sector switches, the “floating gate” (FG) of these memory cells (4) may be short-circuited to the “control gate” (CG).
Claims16
Memory arrangement, comprising a plurality of first memory cells, which are grouped into memory sectors, and in each case are addressable via a word line and connected to at least one bit line for writing and/or reading out digital information, at least one switching means for activating the respective memory sector being allocated to each memory sector, and wherein the switching means are in each case constituted by a second memory cell,
- the second memory cell being an MOS transistor with a floating-gate terminal and a control-gate terminal, the floating-gate terminal being short-circuited to the control-gate terminal.
Memory arrangement according to claim wherein the memory sectors in each case comprise one column of first memory cells.
A method of using a memory arrangement, comprising:
- providing a memory arrangement comprising a plurality of first memory cells, which are grouped into memory sectors, and in each case are addressable via a word line and connected to at least one bit line for writing and/or reading out digital information, wherein a second cell, which belongs to the memory arrangement and is connected to a memory sector, and
- activating the respective memory sector,
- the second cell being a MOS transistor with a floating-gate terminal and a control-gate terminal, the floating-gate terminal being short-circuited to the control-gate terminal.
A method for utilizing a memory cell of a memory arrangement as a sector switch, comprising:
- providing a the memory arrangement comprising a plurality of first memory cells, which are grouped into memory sectors, and in each case are addressable via a word line and connected to at least one bit line for writing and/or reading out digital information;
- activating the respective memory sector with a second cell, which belongs to the memory arrangement and is connected to a memory sector, said second cells being a MOS transistor with a floating-gate terminal and a control-gate terminal, the floating-gate terminal being short-circuited to the control-gate terminal.
Memory arrangement, comprising a plurality of first memory cells, which are grouped into memory sectors, and in each case are addressable via a word line and connected to at least one bit line for writing and/or reading out digital information, at least one switching means for activating the respective memory sector being allocated to each memory sector, and wherein the switching means are in each case constituted by a second memory cell,
- the second memory cell being a MOS transistor formed in a well doped with charge carriers of a first charge-carrier type, the well being in turn formed in a further well doped with charge carriers of a second charge-carrier type and the further well being formed on a substance doped with charge carriers of the first charge-carrier type, the first charge-carrier type being the opposite of the second charge-carrier type.
Dependencies are inferred from the claim text.