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US 6,665,209 B2Granted
Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system
AssigneeRenesas Technology Corp.
InventorsKenichi Osada, Hisayuki Higuchi, Koichiro Ishibashi
Life of this patent
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Abstract
A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.
Claims5
A semiconductor circuit comprising:
- a first memory block having a plurality of first bit lines and a plurality of first SRAM memory cells coupled to said plurality of first bit lines;
- a second memory block having a plurality of second bit lines and a plurality of second SRAM memory cells coupled to said plurality of second bit lines;
- a first and second wiring line each laid over said first and second memory blocks and each extending in the direction of said plurality of first and second bit lines;
- a plurality of first MOSFETs, each having a source/drain path coupled between said first wiring line and each of said plurality of first bit lines,
- a plurality of second MOSFETs, each having a source/drain path coupled between said first wiring line and each of said plurality of second bit lines,
- a plurality of third MOSFETs, each having a source/drain path coupled between said second wiring line and each of said plurality of first bit lines, and
- a plurality of fourth MOSFETs, each having a source/drain path coupled between said second wiring line and each of said plurality of second bit lines.
4 more elements
Dependencies are inferred from the claim text.