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US 6,665,204 B2Granted
Semiconductor memory device for decreasing a coupling capacitance
AssigneeNEC Corporation
InventorKoichi Takeda
Life of this patent
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Abstract
The semiconductor memory device of the present invention comprises: memory cells arranged in a matrix; word lines extending in a row direction; bit line pairs extending in a column direction; exchange blocks for exchanging the bit lines of the different neighboring bit line pairs.
Claims20
A semiconductor memory device comprising:
- memory cells arranged in a matrix;
- word lines extending in a first direction;
- bit line pairs extending in a second direction, perpendicular to said first direction;
- exchange blocks for exchanging the bit lines of different bit line pairs;
- and
- a plurality of memory cell blocks each of which has a predetermined number of the memory cells, and which are aligned in the second direction, wherein the respective exchange blocks are positioned between the memory cell blocks;
- and
- wherein first exchange blocks exchange the bit lines of the different bit line pairs, and second exchange blocks exchange bit lines constituting the same bit line pairs, wherein the first and second exchange blocks are arranged alternately.
5 more elements
In a semiconductor memory device including memory cells arranged in a matrix, and bit line pairs, a method comprising:
- forming memory cell blocks including at least a first, second and third memory cell block, each memory cell block having a predetermined number of the memory cells, and
- exchanging bit lines of different bit line pairs between said first memory cell block and said second memory cell block, and exchanging bit lines constituting the same bit line pairs between said second cell memory block and said third cell memory block.
A semiconductor memory device comprising:
- memory cells arranged in a matrix;
- word lines extending in a first direction;
- bit line pairs extending in a second direction, perpendicular to said first direction;
- exchange blocks for exchanging the bit lines of different bit line pairs;
- and
- a first connection layer for forming the bit lines;
- and a second connection layer for exchanging the bit lines at the exchange blocks.
4 more elements
A semiconductor memory device comprising:
- memory cells arranged in a matrix;
- word lines extending in a first direction;
- bit line pairs extending in a second direction, perpendicular to said first direction;
- exchange blocks for exchanging the bit lines of different bit line pairs;
- and
- wherein the respective bit line pairs are formed in the same connection layer outside the exchange blocks.
3 more elements
A semiconductor memory device comprising:
- memory cells arranged in a matrix;
- word lines extending in a one direction;
- bit line pairs extending in a second direction, perpendicular to said first direction;
- exchange blocks for exchanging the bit lines of different bit line pairs;
- and wherein the respective bit line pairs are formed in a plurality of connection layers outside the exchange blocks.
2 more elements
Dependencies are inferred from the claim text.