Semiconductor memory device having a hierarchial I/O strucuture

A semiconductor memory device comprising:

• a plurality of first memory array areas disposed along a virtual line extending in a first direction;
• a plurality of first sense amplifier areas disposed alternately relative to said plurality of first memory array areas;
• a plurality of first sub common data lines which are provided in association with said plurality of first sense amplifier areas and extend in a second direction intersecting said virtual line;
• a first main common data line extending in the first direction;
• a plurality of first switch circuits respectively provided between said plurality of first sub common data lines and said first main common data line to selectively connect any of said plurality of first sub common data lines to said first main common data line;
• a plurality of second memory array areas respectively disposed along said plurality of first memory array areas;
• a plurality of second sense amplifier areas disposed alternately relative to said plurality of second memory array areas;
• a plurality of second sub common data lines which are provided in association with said plurality of second sense amplifier areas and extend in the second direction;
• a second main common data line extending in the first direction;
• and
• a plurality of second switch circuits respectively provided between said plurality of second sub common data lines and said second main common data line to selectively connect any of said plurality of second sub common data lines to said second main common data line,
• wherein said second main common data line is formed on the one side of portions divided into two with said plurality of first memory array areas as a boundary, and said plurality of second memory array areas are included on the other side.