Video signal processing device that allows an image display device on which pixels are fixed in number to display every video signal

A video signal processing device for displaying, on a display, pixels in a video signal inputted from an image signal source, said video signal processing device comprising:

• a clock delay circuit operable to receive a reference signal, and delay the reference signal by the an odd number of clocks for output as a clock output signal;
• a multiplexer operable to select either the reference signal or the clock output signal from said clock delay circuit for output as a multiplexer output signal;
• an A/D converter operable to convert the video signal into a digital signal for two-phase output including first phase data and second phase data with reference to the multiplexer output signal from said multiplexer;
• a leading edge detection circuit operable to detect, in a predetermined manner, a leading edge of a first valid video signal region in either the first phase data or the second phase data, and outputs a detection signal corresponding thereto;
• a back porch detection circuit operable to detect a back porch period starting from the multiplexer output signal from said multiplexer to the detection signal outputted from said leading edge detection circuit;
• a storage part operable to receive the back porch period, and store and output the back porch period in a separate manner depending on whether the back porch period is based on the reference signal or the clock output signal selected and outputted by said multiplexer as the multiplexer output signal;
• and
• a comparator operable to output a control signal to control said multiplexer to switch the multiplexer output signal selected and outputted therefrom so that said storage part outputs a back porch period corresponding to each of the reference signal and the clock output signal as the multiplexer output signal selected and outputted from said multiplexer, compare the corresponding back porch periods outputted from said storage part with each other, and when the back porch period corresponding to the reference signal as the multiplexer output signal is equal to or shorter than the back porch period corresponding to the clock output signal from said clock delay circuit as the multiplexer output signal, determine that head data in a second valid video signal region in the video signal is included in the first phase data, and output another control signal.

A video signal processing device for displaying, on a display, pixels in a video signal inputted from an image signal source, said video signal processing device comprising:

• a clock delay circuit operable to receive a reference signal, and delay the reference signal by an odd number of clocks for output as a clock output signal;
• a multiplexer operable to select either the reference signal or the clock output signal from said clock delay circuit for output as a multiplexer output signal;
• an A/D converter operable to convert the video signal into a digital signal for two-phase output including first phase data and second phase data with reference to the multiplexer output signal from said multiplexer;
• a leading edge detection circuit operable to detect a leading edge of a first valid video signal region in the first phase data, and outputs a first detection signal corresponding thereto;
• a falling edge detection circuit operable to detect a falling edge of a second valid video signal region in the second phase data, and output a second detection signal corresponding thereto;
• a valid video period detection circuit operable to detect a valid video period starting from the first detection signal outputted from said leading edge detection circuit to the second detection signal outputted from said falling edge detection circuit;
• and
• a comparator operable to compare a value half of an inputted horizontal resolution with the valid video period, and when the value half of the horizontal resolution is larger than the valid video period in value, determine that head data in a third valid video signal region in the video signal is not included in the first phase data, and output a signal to control said multiplexer to switch the multiplexer output signal therefrom.

A video signal processing device for displaying, on a display, pixels in a video signal inputted from an image signal source, said video signal processing device comprising:

• a clock delay circuit operable to receive a reference signal, and delay the reference signal by an odd number of clocks for output as a clock output signal;
• a multiplexer operable to select either the reference signal or the clock output signal from said clock delay circuit for output as a multiplexer output signal;
• an A/D converter operable to convert the said video signal into a digital signal for two-phase output including first phase data and second phase data with reference to the multiplexer output signal from said multiplexer;
• a leading edge detection circuit operable to detect a leading edge of a second valid video signal region in the second phase data, and outputs a second detection signal corresponding thereto;
• a falling edge detection circuit operable to detect a falling edge of a first valid video signal region in the first phase data, and outputs a first detection signal corresponding thereto;
• a valid video period detection circuit operable to detect a valid video period starting from the second detection signal outputted from said leading edge detection circuit to the first detection signal outputted from said falling edge detection circuit;
• and
• a comparator operable to compare a value half of an inputted horizontal resolution with the valid video period, and when the value half of the horizontal resolution is smaller than the valid video period in value, determine that head data in a third valid video signal region in the video signal is not included in the first phase data, and output a signal to control said multiplexer to switch the multiplexer output signal therefrom.

A video signal processing device for displaying, on a display, pixels in a video signal inputted from an image signal source, said video signal processing device comprising:

• a clock delay circuit operable to receive a reference signal, and delay the reference signal by an odd number of clocks for output as a clock output signal;
• a multiplexer operable to select either the reference signal or the clock output signal from said clock delay circuit for output as a multiplexer output signal;
• an A/D converter operable to convert the video signal into a digital signal for two-phase output including first phase data and second phase data with reference to the multiplexer output signal from said multiplexer;
• a first leading edge detection circuit operable to detect a leading edge of a first valid video signal region in the first phase data, and output a first leading edge detection signal corresponding thereto;
• a second leading edge detection circuit operable to detect a leading edge of a second valid video signal region in the second phase data, and output a second leading edge detection signal corresponding thereto;
• a first falling edge detection circuit operable to detect a falling edge of the second valid video signal region in the second phase data, and output a first falling edge detection signal corresponding thereto;
• a second falling edge detection circuit operable to detect a falling edge of the first valid video signal region in the first phase data, and output a second falling edge detection signal corresponding thereto;
• a first valid video period detection circuit operable to detect a first valid video period starting from the first leading edge detection signal outputted from said first leading edge detection circuit to the first falling edge detection signal outputted from said first falling edge detection circuit;
• a second valid video period detection circuit operable to detect a second valid video period starting from the second leading edge detection signal outputted from said second leading edge detection circuit to the second falling edge detection signal outputted from said second falling edge detection circuit;
• and
• a comparator operable to compare the first valid video period and the second valid video period, and when the second valid video period is longer than the first valid video period, determine that head data in a third valid video signal region in the video signal is not included in the first phase data, and output a signal to control said multiplexer to switch the multiplexer output signal therefrom.

A video signal processing device for displaying, on a display, pixels in a video signal inputted from an image signal source, said video signal processing device comprising:

• an A/D converter operable to convert the video signal into a digital signal for two-phase output including first phase data and second phase data with reference to an incoming reference signal;
• a clock delay circuit to receive the second phase data, and delay the second phase data by an odd number of clocks for output as a clock output signal;
• a first multiplexer operable to select either the first phase data or the clock output signal from said clock delay circuit for output as a first multiplexer output signal;
• a second multiplexer operable to select either the second phase data or the first phase data for output as a second multiplexer output signal;
• a first leading edge detection circuit operable to detect a leading edge of a first valid video signal region in the first phase data, and outputs a first detection signal corresponding thereto;
• a second leading edge detection circuit operable to detect a leading edge of a second valid video signal region in the second phase data, and output a second detection signal corresponding thereto;
• a first back porch detection circuit operable to detect a first back porch period starting from the reference signal to the first detection signal outputted from said first leading edge detection circuit;
• a second back porch detection circuit operable to detect a second back porch period starting from the reference signal to the second detection signal outputted from said second leading edge detection circuit;
• and
• a comparator operable to compare the first back porch period and the second back porch period, and when the first back porch period is longer than the second back porch period, determine that head data in a third valid video signal region in the video signal is not included in the first phase data, and output a signal to control said first and second multiplexers to switch the first multiplexer output signal and second multiplexer output signal simultaneously, wherein
• right after activation of said video signal processing device, said first multiplexer selects the first phase data for output as the first multiplexer output signal, and said second multiplexer selects the second phase data for output as the second multiplexer output signal.