Digital/analog converter circuit, level shift circuit, shift register utilizing level shift circuit, sampling latch circuit, latch circuit and liquid crystal display device incorporating the same

A liquid crystal display device having a first board formed by an effective pixel area comprising a plurality of pixels and a drive circuit containing a digital/analog converter circuit for converting an n-bit (n is an integer of 2 or more) digital data signal, a second board placed at a specified gap facing said first board, and a liquid crystal layer held between said first and said second boards,

• wherein said digital/analog converter circuit comprises 2n step select units connected across 2n reference voltage lines and pixel section column lines, each step select unit including n serially connected analog switches polarized to match a logic state of each bit of the n-bit digital data signal,
• a shift register including a plurality of transfer stages to output sampling pulses in sequence from each transfer stage by performing a shift operation in response to a start signal;
• a first latch circuit to synchronize with the sampling pulses output from each transfer stage and sequentially sample and latch the digital data signals;
• and
• a second latch circuit to latch the signal sequentially sampled in said first latch circuit with a matching column line at each one horizontal period and supply the latched signal to said digital/analog conversion circuit,
• wherein said shift register includes a first level shift circuit to supply the start signal to an initial stage of the transfer stages and a second level shift circuit to supply clock signals to each of the transfer stages as a level shift, the first and second level shift circuits including a CMOS latch cell having two input sections and a resistor element inserted between each of the two input sections and two signal sources and
• wherein said first latch circuit includes a CMOS latch cell having two input sections and a first switch connected between the two input sections and two input signal sources of the said CMOS latch cell, a second switch connected between a power supply line and a power supply side of said CMOS latch cell and, a control means to control complementary switching of said first and said second switches and,
• wherein said second latch circuit includes a CMOS latch cell having two input sections and a first switch and a second switch installed on at least one of a positive power supply or negative power supply side of the CMOS latch to respectively select a first and a second power supply having different power supply voltages and, a control means to control switching of said first and second switches according to each period of latch operation and output operation of the CMOS latch cell.

A liquid crystal display device integrated with a pixel section and drive circuit containing scanning system onto a single substrate, said liquid crystal display device having a scan system comprising:

• a plurality of transfer stages;
• a first level shift circuit to supply a start signal as a level shift to a first stage of the transfer stages;
• and
• a second level shift circuit to supply a clock signal as a level shift to each of the transfer stages,
• wherein said first and second level shift circuits include a CMOS latch cell having two input sections and a first resistor element inserted between each of the two input sections and two input signal sources.

A liquid crystal display device comprising:

• a pixel section and drive circuit containing scanning system;
• said scanning system including a latch cell, said latch cell having a plurality of inverters, said plurality of inverters including a first inverter and a second inverter,
• a first input signal being supplied to an input of said first inverter while a second input signal is supplied to an input of said second inverter,
• a voltage potential being supplied to said first and second inverters while said first and second input signals are isolated from said first and second inverters,
• said voltage potential being isolated from said first and second inverters while said first and second input signals are supplied to said first and second inverters.