US 6,664,859 B1Granted

State machine based phase-lock-loop for USB clock recovery

AssigneeFaaday Technology Crop.

InventorsJen-Ying Chen, Gow-Jeng Lin, Chien-Ming Chen

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Abstract

A single mode state machine for recovering the Universal Serial Bus (USB) clock from the USB. The claimed state machine running at 4X speed includes only five states and generates a 1X speed clock. When transmitting, the claimed invention acts as a divide-by-four counter and divides the 4X clock into a 1X clock to be used by control logic (for example, a Serial Interface Engine). When receiving, the same state group acts as a divide-by-four counter with the received data's status being continuously monitored to reset the state machine to an original state to dynamically adjust the duty cycle of the receiving clock. The exact selection of transition path is determined by the logical AND of a phase change within the data and a signal indicating whether the state machine is currently transmitting or receiving.

Claims20

Dependent claims

An apparatus comprising a phase-lock-loop state machine for generating a digital clock signal, the phase-lock-loop state machine comprising:

a first state for serving as an entry point after a reset and for generating a first clock signal;
a second state for generating a second clock signal;
a third state for generating the second clock signal;
a fourth state for generating the first clock signal;
a fifth state for generating the first clock signal;
a transition from the first state to the second state on a first control signal;
a transition from the first state to the fifth state on a second control signal;
a transition from the second state to the third state on the first control signal;
a transition from the second state to the fifth state on the second control signal;
a transition from the third to the fourth state on the first control signal;
a transition from the third state to the fifth state on the second control signal;
a transition from the fourth state to the first state on the first control signal;
a transition from the fourth state to the fifth state on the second control signal;
and
a transition from the fifth state to the first state on the first control signal;
wherein transitions between the states occur at a predetermined frequency.

13 more elements

A method for synchronizing a receiving clock with a transmitting clock, the receiving clock comprising a control circuit and a five-state phase-lock-loop state machine to generate the receiving clock signal at one-fourth the frequency of an externally generated clock, the method comprising:

the control circuit generating a first control signal if a phase change in data being received has occurred and generating a second control signal if a phase change in the data being received has not occurred;
if in a first state, transitioning from the first state to a second state on the first control signal;
if in the first state, transitioning from the first state to a fifth state on the second control signal;
if in the second state, transitioning from the second state to a third state on the first control signal;
if in the second state, transitioning from the second state to the fifth state on the second control signal;
if in the third state, transitioning from the third to a fourth state on the first control signal;
if in the third state, transitioning from the third state to the fifth state on the second control signal;
if in the fourth state, transitioning from the fourth state to the first state on the first control signal;
if in the fourth state, transitioning from the fourth state to the fifth state on the second control signal;
and
if in the fifth state, transitioning from the fifth state to the first state on the first control signal;
and outputting the receiving clock signal according to the current state of the phase-lock-loop state machine.

9 more elements

Dependencies are inferred from the claim text.