FET active load and current source
AssigneeInphi Corporation
InventorCarl Walter Pobanz
Life of this patent
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Abstract
The present invention is a circuit comprising two series-coupled field effect transistor (FET) devices with a resistor network coupled in parallel forming a composite device (that can be substituted directly for a single FET device). In applications such as active loads or current sources, the composite device exhibits a greater breakdown voltage and superior high-frequency characteristics. The resistor network provides optimum direct current (DC) bias for depletion mode devices and superior high-frequency loading. Bandwidth and stability are both increased. Furthermore, this circuit is compatible with depletion mode FET processes having a single fixed threshold voltage.
Claims16
A voltage follower circuit, comprising:
- a first field effect transistor (FET) having a source, a drain, and a gate, said drain connected to a first supply voltage;
- a second FET having a source, a drain, and a gate, the drain of the second FET connected to the source of the first FET, the gate of said second FET providing an input for said voltage follower circuit and the source of said second FET providing an output for said voltage follower circuit;
- a resistive network having a first resistor and a second resistor, each of which has first and second terminals, the first terminal of said first resistor connected to said first supply voltage, the second terminal of the first resistor coupled with the first terminal of the second resistor, the gate of the second FET coupled to the second terminal of the second resistor, and the gate of the first FET coupled to the second terminal of the first resistor;
- and
- a current source connected between the source of said second FET and a second supply voltage such that the voltage at said output follows a voltage applied at said input.
A field-effect transistor (FET) circuit suitable for use as an active load or current source, comprising:
- a first FET having its drain connected to a first terminal;
- a second FET having its drain connected to the source of said first FET, and its gate and source directly connected to a second terminal;
- a first resistor connected between said first terminal and the gate of said first FET;
- and
- a second resistor connected between the gate of said first FET and the gate of said second FET.
A differential amplifier with an active load, comprising:
- a differential transistor pair comprising first and second transistors having their current circuits connected together at a common node;
- a bias current source connected between said common node and a first supply voltage;
- and
- an active load connected between a second supply voltage and the output of one of said pair transistors, said active load comprising:
- a first field-effect transistor (FET) having its drain connected to a first terminal;
- a second FET having its drain connected to the source of said first FET and its gate and source connected to a second terminal;
- a first resistor connected between said first terminal and the gate of said first FET;
- and
- a second resistor connected between the gate of said first FET and the gate of said second FET;
- said first terminal connected to said second supply voltage and said second terminal connected to said pair transistor output.
A differential amplifier, comprising:
- a differential transistor pair comprising first and second transistors having their current circuits connected together at a common node;
- a bias current source connected between said common node and a supply voltage, said bias current source comprising:
- a first field-effect transistor (FET) having its drain connected to a first terminal;
- a second FET having its drain connected to the source of said first FET and its gate and source connected to a second terminal;
- a first resistor connected between said first terminal and the gate of said first FET;
- and
- a second resistor connected between the gate of said first FET and the gate of said second FET;
- said first terminal connected to said common node and said second terminal connected to said supply voltage.
Dependencies are inferred from the claim text.